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Nuno Lourenço received the Licenciado, M.Sc., and Ph.D. degrees in Electrical and Computer Engineering from Instituto Superior Técnico, University of Lisbon, Portugal 2005, 2007, and 2014 respectively. He is an Assistant Professor at the Department of Electrical and Computer Engineering of IST-UL since 2023 and conduct his research at Instituto de Telecomunicações in Lisbon since 2005. He was an Invited Assistant Professor at the Informatics Department of the School of Sciences and Technology of the University of Évora, from 2021 to 2024. He has authored or co-authored over 100 international scientific publications, including two patents, eight books, three book chapters, 35 international journals, and over 50 international conference papers, and is the supervisor in 3 ongoing Ph.D. theses and several ongoing and completed M.Sc. dissertations. He was the General Chair for the 2022 edition of the International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD). He was involved in the Organizing Committee of several International Conferences such as IEEE ISCAS'15, PRIME'16-21 or SMACD'16-21, and he was the General Chair of SMACD 2022 and Publication Chair of the SMACD 2016, 2017, 2019, and 2021, and, of Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) 2016, 2019, and 2021, both technically sponsored by IEEE, IEEE CEDA, and IEEE CAS societies. He has received 13 Scientific Awards and Distinctions, including several "best paper awards," the "Best EDA tool" from SMACD'15 competition, and the "IET DesignVision Award in the category of Semiconductor IP." He has participated in several Scientific projects with national and international Universities and Companies, and he is the Principal Investigator of the ongoing internal HAICAS project funded by IT. His current research interests include AMS/RF IC design, Artificial Intelligence (Evolutionary Computation and Machine Learning) applied to Electronic Design Automation.
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Identificação

Identificação pessoal

Nome completo
Nuno Calado Correia Lourenço

Nomes de citação

  • Lourenço, Nuno
  • N. Lourenço
  • N. C. C. Lourenço
  • Nuno Lourenco
  • N. Lourenco
  • Nuno Lourenço

Identificadores de autor

Ciência ID
AA17-A737-37DC
ORCID iD
0000-0002-9625-6435
Google Scholar ID
Zu5PfIYAAAAJ
Researcher Id
L-8474-2015
Scopus Author Id
54880249500

Moradas

  • Instituto de Telecomunicações, Instituto Superior Técnico. Av.ª Rovisco Pais, 1049 001, Lisboa, Lisboa, Portugal (Profissional)

Websites

Domínios de atuação

  • Ciências da Engenharia e Tecnologias - Engenharia Eletrotécnica, Eletrónica e Informática

Idiomas

Idioma Conversação Leitura Escrita Compreensão Peer-review
Português (Idioma materno)
Inglês Utilizador proficiente (C1) Utilizador proficiente (C1) Utilizador proficiente (C1) Utilizador proficiente (C1) Utilizador proficiente (C1)
Romeno Utilizador independente (B1) Utilizador elementar (A2) Utilizador elementar (A1) Utilizador elementar (A2) Utilizador elementar (A1)
Formação
Grau Classificação
2014
Concluído
 Engenharia Electrotécnica e de Computadores (Doutoramento)
Universidade de Lisboa Instituto Superior Técnico, Portugal
"Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects" (TESE/DISSERTAÇÃO)
 Aprovado com Muito Bom com Distinção
2007
Concluído
 Engenharia Electrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
"LayGen - Automatic Layout Generation of Analog ICs based on Hierarchical Template Descriptions and Intelligent Computing Techniques" (TESE/DISSERTAÇÃO)
 Aprovado (Média da parte escolar: 4 Valores )
2005
Concluído
 Engenharia Electrotécnica e de Computadores (Licenciatura)
Universidade de Lisboa Instituto Superior Técnico, Portugal
"LayGen - Automatic Analog IC Layout Generator" (TESE/DISSERTAÇÃO)
 15
Percurso profissional

Ciência

Categoria Profissional
Instituição de acolhimento 		Empregador
2019/01/02 - Atual Investigador (Investigação) Instituto de Telecomunicações, Portugal
2015/01/01 - 2018/12/31 Pós-doutorado (Investigação) Fundação para a Ciência e a Tecnologia, Portugal
Instituto de Telecomunicações, Portugal
2011/04/01 - 2014/12/31 Investigador (Investigação) Fundação para a Ciência e a Tecnologia, Portugal
Instituto de Telecomunicações, Portugal

Docência no Ensino Superior

Categoria Profissional
Instituição de acolhimento 		Empregador
2023/10/01 - Atual Professor Auxiliar (Docente Universitário) Universidade de Lisboa Instituto Superior Técnico, Portugal
Universidade de Lisboa Instituto Superior Técnico, Portugal
2021/07/13 - 2022/08/13 Professor Auxiliar Convidado (Docente Universitário) Universidade de Évora Escola de Ciências e Tecnologia, Portugal
2015 - 2019 Professor Auxiliar Convidado (Docente Universitário) Universidade de Lisboa Instituto Superior Técnico, Portugal
2005 - 2006 Monitor (Docente Universitário) Universidade de Lisboa Instituto Superior Técnico, Portugal

Outros

Categoria Profissional
Instituição de acolhimento 		Empregador
2006/06/01 - 2011/03/31 Engineering Manager / Digital IC Design Coreworks S.A., Portugal
Projetos

Projeto

Designação Financiadores
2023/05/01 - 2026/04/30 Generative AI for Analog Chip Design
IT/SONY_AVGS
Investigador responsável
Instituto de Telecomunicações, Portugal
 Sony Advanced Visual Sensing AG
Em curso
2020/01/01 - 2022/12/31 PROMISE - PROgrammable MIxed Signal Electronics
870358
Investigador Pós-doutorado
Instituto de Telecomunicações, Portugal
 European Commission
Em curso
2020/05/01 - 2022/04/30 HAICAS - Hierarchical Analog IC Automatic Synthesis
UIDB/EEA/50008/2020
Investigador responsável
Instituto de Telecomunicações, Portugal
 Instituto de Telecomunicações
Em curso
2020/02/01 - 2022/01/31 LAY(RF)^2 - Ready-to-Fabricate RF and mmWave Integrated Circuit Layouts
UIDB/EEA/50008/2020
Investigador Pós-doutorado
Instituto de Telecomunicações, Portugal
 Instituto de Telecomunicações
Em curso
2013/10/01 - 2021/11/01 AIDA-C - Analog IC Optimizer
S01001
Investigador
Instituto de Telecomunicações, Portugal
 Thales Alenia Space
Em curso
2016 - 2018 RAPID - RF IC Design Automation
UID/EEA/50008/2013
Investigador Pós-doutorado
Instituto de Telecomunicações, Portugal
Concluído
2013/04/01 - 2016/03/31 DISRUPTIVE - A PARADIGM SHIFT IN THE DESIGN OF ANALOG AND MIXED-SIGNAL NANOELECTRONIC CIRCUITS AND SYSTEMS
EXCL/EEI-ELC/0261/2012
Investigador
Instituto de Telecomunicações, Portugal
 Fundação para a Ciência e a Tecnologia
Concluído
2014/03/01 - 2016/01/31 OPERA - Layout-Aware Analog IC Design Automation
PEst-OE/EEI/LA0008/2013
Investigador Pós-doutorado
Instituto de Telecomunicações, Portugal
Concluído
2011 - 2013 AIDA - Automated P-Cell Generation based on Multi-Objective Optimization and Pareto Optimal Front Circuit Level Characterization
P01112
Investigador
Instituto de Telecomunicações
2006 - 2008 LAYGEN - Automatic Layout Generation of Mixed-Signal ICs
IT/LA346/2006
Investigador
Instituto de Telecomunicações, Portugal
 Instituto de Telecomunicações
Concluído
2005 - 2007 EVOLUTION - Application Techniques in Evolutionary Computation Methods Automation Project Analog Integrated Circuit
POSC/EEA/60225/2004
Investigador
Fundação para a Ciência e a Tecnologia
Produções

Publicações

Artigo em conferência
  1. Passos, Fábio; Nuno Lourenço; Mendes, Luís; Martins, Ricardo; Vaz, João; Horta, Nuno. "A 23.5–32.5GHz, 17dBm PSAT and 37.5% PAE Power Amplifier Synthesized Using an Automated Design Methodology". 2023.
    10.1109/smacd58065.2023.10192226
  2. Amaral, André; Gusmão, António; Vieira, Rafael; Martins, Ricardo; Horta, Nuno; Nuno Lourenço. "An ANN-Based Approach to the Modelling and Simulation of Analogue Circuits". 2023.
    10.1109/smacd58065.2023.10192134
  3. Vieira, Rafael; Martins, Ricardo; Horta, Nuno; Nuno Lourenço. "Design Space Exploration of Single-Stage OTAs towards an Ultra-Low-Power LNA for ECG Signals". 2023.
    10.1109/smacd58065.2023.10192218
  4. Passos, F.; Nuno Lourenço; Mendes, L.; Martins, R.; Vaz, J.; Horta, N.. "Efficient Hierarchical mm-Wave System Synthesis with Embedded Accurate Transformer and Balun Machine Learning Models". Tokio, 2023.
    10.1145/3566097.3567879
  5. Domingues, Joao; Gusmao, Antonio; Horta, Nuno; Lourenco, Nuno; Martins, Ricardo. "Accelerating Voltage-Controlled Oscillator Sizing Optimizations with ANN-based Convergence Classifiers and Frequency Guess Predictors". 2022.
    10.1109/smacd55068.2022.9816265
  6. Vieira, Rafael; Passos, Fabio; Povoa, Ricardo; Martins, Ricardo; Horta, Nuno; Guilherme, Jorge; Lourenco, Nuno. "Architectural Design for Heartbeat Detection Circuits using Verilog-A Behavioral Modeling". 2022.
    10.1109/smacd55068.2022.9816253
  7. Alves, Pedro; Gusmao, Antonio; Horta, Nuno; Lourenco, Nuno; Martins, Ricardo. "ANN-based Analog IC Floorplan Recommender with a Broader Topological Constraints Coverage". 2022.
    10.1109/smacd55068.2022.9816195
  8. Lourenco, Nuno; Passos, Fabio; Vieira, Rafael; Martins, Ricardo; Horta, Nuno; Guilherme, Jorge; Povoa, Ricardo. "Radiation-Hardened Bandgap Voltage and Current Reference for Space Applications with 2.38 ppm/°C Temperature Coefficient". 2022.
    10.1109/smacd55068.2022.9816300
  9. Passos, F.; Lourenco, N.; Martins, R.; Roca, E.; Castro-Lopez, R.; Horta, N.; Fernandez, F. V.. "Machine Learning Approaches for Transformer Modeling". 2022.
    10.1109/smacd55068.2022.9816303
  10. Luís Miguel Moreira Mendes; Caldinhas Vaz, João; Fábio Moreira de Passos; Lourenço, Nuno; Ricardo Miguel Ferreira Martins. "Automatic Design of High-Gain 26.5-to-29.5-GHz Transformer-Less Low-Noise Amplifier 1.86-to-8.87-mW Variants in 65-nm CMOS". Trabalho apresentado em IEEE International Symposium on Circuits & Systems (ISCAS), Austin, 2022.
  11. Vaz, Pedro; Gusmao, Antonio; Horta, Nuno; Nuno Lourenço; Martins, Ricardo. "Speeding-Up Complex RF IC Sizing Optimizations with a Process, Voltage and Temperature Corner Performance Estimator based on ANNs". Trabalho apresentado em IEEE International Symposium on Circuits and Systems (IEEE ISCAS), 2022.
    10.1109/iscas48785.2022.9937911
  12. Gusmao, Antonio; Horta, Nuno; Lourenco, Nuno; Martins, Ricardo; Gusmao, A.; Horta, N.; Lourenco, N.; Martins, R.. "Late Breaking Results: Attention in Graph2Seq Neural Networks towards Push-Button Analog IC Placement". 2021.
    10.1109/dac18074.2021.9586177
  13. Rafael Vieira; N. Lourenço; Ricardo Filipe Sereno Póvoa; Nuno Cavaco Gomes Horta; Ricardo Martins; Vieira, R.; Martins, R.; et al. "A Sub-1µA Low-Power Low-Noise Amplifier with Tunable Gain and Bandwidth for EMG and EOG Biopotential Signals". Trabalho apresentado em 16th Conference on PhD Research in Microelectronics and Electronics, 2021.
    Submetido
  14. António Gusmão; Nuno Cavaco Gomes Horta; N. Lourenço; Ricardo Martins. "Late Breaking Results: Attention in Graph2Seq Neural Networks towards Push-Button Analog IC Placement". Trabalho apresentado em Design Automation Conference 2021, 2021.
    Submetido
  15. Martins, R.; Gusmão, A.; Canelas, A.; Passos, F.; Lourenço, N.; Horta, N.. "An Essay on the Next Generation of Performance-driven Analog/RF IC EDA Tools: The Role of Simulation-based Layout Optimization". Trabalho apresentado em IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, 2021.
  16. L. Mendes; J. Vaz; F. Passos; Lourenço, Nuno; R. M. F. Martins. "Design Space Exploration of 26.5-to-29.5-GHz Low-Noise Amplifiers for Low-Power mmWave 5G Communications in 65-nm CMOS". Trabalho apresentado em International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Erfurt, 2021.
    Submetido
  17. Gusmão, A.; Canelas, A.; Horta, N.; Lourenço, N.; Martins, R.. "A deep learning toolbox for analog integrated circuit placement". 2021.
  18. Gusmão, A.; Horta, N.; Lourenço, N.; Martins, R.. "Bringing structure into analog IC placement with relational graph convolutional networks". 2021.
  19. Gusmão, A.; Passos, F.; Póvoa, R.; Horta, N.; Lourenço, N.; Martins, R.; Gusmão, António; et al. "Semi-supervised artificial neural networks towards analog IC placement recommender". Trabalho apresentado em IEEE International Symposium on Circuits and Systems (IEEE ISCAS), Seville, 2020.
  20. Lourenco, N.; Afacan, E.; Martins, R.; Passos, F.; Canelas, A.; Povoa, R.; Horta, N.; Dundar, G.. "Using Polynomial Regression and Artificial Neural Networks for Reusable Analog IC Sizing". Trabalho apresentado em (SMACD), Lausanne, 2019.
    10.1109/smacd.2019.8795282
  21. Martins, Ricardo; Lourenco, Nuno; Horta, Nuno; Yin, Jun; Mak, Pui-In; Martins, Rui P.. "Using EDA Tools to Push the Performance Boundaries of an Ultralow-Power IoT-VCO at 65nm". Trabalho apresentado em (SMACD), 2019.
    10.1109/smacd.2019.8795240
  22. Martins, Ricardo; Lourenço, Nuno; Povoa, Ricardo; Horta, Nuno. "On the Exploration of Design Tradeoffs in Analog IC Placement with Layout-dependent Effects". Trabalho apresentado em (SMACD), 2019.
    10.1109/smacd.2019.8795297
  23. Lourenco, Nuno; Martins, Ricardo; Canelas, Antonio; Povoa, Ricardo; Horta, Nuno; Moutaye, Emanuel. "Hard and Soft Constraints for Multi-objective Analog IC Sizing Optimization". Trabalho apresentado em (SMACD), 2019.
    10.1109/smacd.2019.8795220
  24. Guerra, Daniel; Canelas, Antonio; Povoa, Ricardo; Horta, Nuno; Lourenço, Nuno; Martins, Ricardo. "Artificial Neural Networks as an Alternative for Automatic Analog IC Placement". Trabalho apresentado em (SMACD), 2019.
    10.1109/smacd.2019.8795267
  25. Povoa, Ricardo; Canelas, Antonio; Martins, Ricardo; Horta, Nuno; Lourenço, Nuno; Goes, Joao. "A Low Noise CMOS Inverter-Based OTA for and Healthcare Signal Receivers". Trabalho apresentado em (SMACD), 2019.
    10.1109/smacd.2019.8795248
  26. Lourenco, Nuno; Rosa, Joao; Martins, Ricardo; Aidos, Helena; Canelas, Antonio; Povoa, Ricardo; Horta, Nuno. "On the Exploration of Promising Analog IC Designs via Artificial Neural Networks". Trabalho apresentado em (SMACD), Prague, 2018.
    10.1109/smacd.2018.8434896
  27. Passos, F.; Martins, R.; Lourenco, N.; Roca, E.; Castro-Lopez, R.; Povoa, R.; Canelas, A.; Horta, N.; Fernandez, F.V.. "Handling the Effects of Variability and Layout Parasitics in the Automatic Synthesis of LNAs". Trabalho apresentado em (SMACD), Prague, 2018.
    Publicado • 10.1109/smacd.2018.8434887
  28. Martins, Ricardo; Lourenco, Nuno; Horta, Nuno; Yin, Jun; Mak, Pui-In; Martins, Rui P.. "Design and Optimization of a Class-C/D VCO for Ultra-Low-Power IoT and Cellular Applications". Trabalho apresentado em (SMACD), 2018.
    10.1109/smacd.2018.8434853
  29. Canelas, Antonio; Povoa, Ricardo; Martins, Riccardo; Lourenco, Nuno; Guilherme, Jorge; Horta, Nuno. "A 20 DB Gain Two-Stage Low-Noise Amplifier with High Yield for 5 GHz Applications". Trabalho apresentado em (SMACD), 2018.
    10.1109/smacd.2018.8434917
  30. Pessoa, Tiago; Lourenco, Nuno; Martins, Ricardo; Povoa, Ricardo; Horta, Nuno. "Enhanced analog and RF IC sizing methodology using PCA and NSGA-II optimization kernel". Trabalho apresentado em (DATE), Dresden, 2018.
    10.23919/date.2018.8342092
  31. Martins, R.; Lourenco, N.; Povoa, R.; Canelas, A.; Horta, N.; Passos, F.; Castro-Lopez, R.; Roca, E.; Fernandez, F.. "Layout-aware challenges and a solution for the automatic synthesis of radio-frequency IC blocks". Trabalho apresentado em (SMACD), 2017.
    10.1109/SMACD.2017.7981577
  32. Canelas, Antonio; Martins, Ricardo; Povoa, Ricardo; Lourenco, Nuno; Horta, Nuno. "Efficient yield optimization method using a variable K-Means algorithm for analog IC sizing". Trabalho apresentado em (DATE), 2017.
    10.23919/DATE.2017.7927171
  33. Lourenco, N.; Martins, R.; Povoa, R.; Canelas, A.; Horta, N.; Passos, F.; Castro-Lopez, R.; Roca, E.; Fernandez, F.V.. "New mapping strategies for pre-optimized inductor sets in bottom-up RF IC sizing optimization". 2017.
    10.1109/SMACD.2017.7981582
  34. Cachaco, Jose; Machado, Nuno; Lourenco, Nuno; Guilherme, Jorge; Horta, Nuno. "Automatic technology migration of analog IC designs using generic cell libraries". Trabalho apresentado em (DATE), 2017.
    10.23919/DATE.2017.7927189
  35. Povoa, R.; Canelas, A.; Martins, R.; Lourenco, N.; Horta, N.; Goes, J.. "A dynamic voltage-combiners biased OTA for low-power and high-speed SC circuits". Trabalho apresentado em (PRIME), 2017.
    10.1109/PRIME.2017.7974122
  36. Passos, F.; Roca, E.; Castro-Lopez, R.; Fernandez, F.V.; Martins, R.; Lourenco, N.; Povoa, R.; Canelas, A.; Horta, N.. "Systematic design of a voltage controlled oscillator using a layout-aware approach". Trabalho apresentado em (SMACD), 2017.
    10.1109/SMACD.2017.7981580
  37. Canelas, Antonio; Martins, Ricardo; Povoa, Ricardo; Lourenco, Nuno; Horta, Nuno. "Yield optimization using k-means clustering algorithm to reduce Monte Carlo simulations". Trabalho apresentado em (SMACD), 2016.
    10.1109/SMACD.2016.7520729
  38. Martins, Ricardo; Canelas, Antonio; Lourenco, Nuno; Horta, Nuno. "On-the-fly exploration of placement templates for analog IC layout-aware sizing methodologies". Trabalho apresentado em (SMACD), 2016.
    10.1109/SMACD.2016.7520731
  39. Neves, David; Martins, Ricardo; Lourenço, Nuno; Horta, Nuno; Neves, D.; Martins, R.; Lourenço, N.; Horta, N.. "Design Automation Tasks Scheduling for Enhanced Parallel Execution of a State-of-the-Art Layout-Aware Sizing Approach". Trabalho apresentado em (DATE), 2016.
    10.3850/9783981537079_0860
  40. Martins, Ricardo; Lourenco, Nuno; Horta, Nuno; Guerreiro, Nuno; Santos, Marcelino. "Embedding Fault List Compression techniques in a design automation framework for analog and Mixed-Signal structural testing". Trabalho apresentado em (DCIS), 2016.
    10.1109/DCIS.2015.7388584
  41. Ferreira, Andre; Lourenco, Nuno; Martins, Ricardo; Horta, Nuno. "Automated analog IC design constraints generation for a layout-aware sizing approach". Trabalho apresentado em (SMACD), 2016.
    10.1109/SMACD.2016.7520740
  42. Cardoso, Bruno; Martins, Ricardo; Lourenco, Nuno; Horta, Nuno. "AIDA-PEx: Accurate parasitic extraction for layout-aware analog integrated circuit sizing". Trabalho apresentado em (PRIME), 2015.
    10.1109/PRIME.2015.7251351
  43. Martins, Ricardo; Lourenco, Nuno; Horta, Nuno. "Analog IC placement using absolute coordinates and a hierarchical combination of Pareto optimal fronts". Trabalho apresentado em (PRIME), 2015.
    10.1109/PRIME.2015.7251334
  44. Povoa, R.; Lourenco, N.; Horta, N.; Goes, J.. "A voltage-combiners-biased amplifier with enhanced gain and speed using current starving". 2015.
    10.1109/ISCAS.2015.7169085
  45. Povoa, R.; Lourenco, N.; Horta, N.; Santos-Tavares, R.; Goes, J.. "A cascode-free single-stage amplifier using a fully-differential folded voltage-combiner". Trabalho apresentado em (ICECS), 2015.
    10.1109/ICECS.2014.7049972
  46. Martins, R.; Lourenco, N.; Canelas, A.; Povoa, R.; Horta, N.. "AIDA: Robust layout-aware synthesis of analog ICs including sizing and layout generation". 2015.
    10.1109/SMACD.2015.7301703
  47. Martins, R.; Povoa, R.; Lourenco, N.; Horta, N.. "Exploring design tradeoffs in analog IC placement with current-flow & current-density considerations". 2015.
    10.1109/SMACD.2015.7301697
  48. Neves, D.; Lourenco, N.; Horta, N.. "Scheduling evaluation tasks for increased efficiency of parallel analog IC synthesis". 2015.
    10.1109/SMACD.2015.7301700
  49. Martins, R.; Lourenco, N.; Canelas, A.; Horta, N.. "Extraction and application of wiring symmetry rules to route analog multiport terminals". 2015.
    10.1109/ISCAS.2015.7169054
  50. Pandey, M.; Canelas, A.; Povoa, R.; Torres, J.; Freire, J.C.; Lourenco, N.; Horta, N.. "Grounded active inductors design optimization for fQmax = 14.2GHz using a 130 nm CMOS technology". 2015.
    10.1109/SMACD.2015.7301693
  51. Lourenco, N.; Martins, R.; Horta, N.; Lourenço, Nuno; Martins, Ricardo; Horta, Nuno. "Layout-aware sizing of analog ICs using floorplan & routing estimates for parasitic extraction". Trabalho apresentado em (DATE), 2015.
    10.7873/DATE.2015.0411
  52. Martins, R.; Lourenco, N.; Canelas, A.; Horta, N.. "Electromigration-aware and IR-Drop avoidance routing in analog multiport terminal structures". 2014.
    10.7873/DATE2014.023
  53. Povoa, R.; Lourenco, R.; Lourenco, N.; Canelas, A.; Martins, R.; Horta, N.. "LC-VCO automatic synthesis using multi-objective evolutionary techniques". 2014.
    10.1109/ISCAS.2014.6865123
  54. Povoa, R.; Lourenco, N.; Horta, N.; Santos-Tavares, R.; Goes, J.. "Single-stage amplifiers with gain enhancement and improved energy-efficiency employing voltage-combiners". 2013.
    10.1109/VLSI-SoC.2013.6673238
  55. Martins, R.; Lourenco, N.; Canelas, A.; Horta, N.. "Multi-port multi-terminal analog router based on an evolutionary optimization kernel". 2013.
    10.1109/CEC.2013.6557907
  56. Rocha, F.; Lourenco, N.; Povoa, R.; Martins, R.; Horta, N.. "A new metaheuristc combining gradient models with NSGA-II to enhance analog IC synthesis". 2013.
    10.1109/CEC.2013.6557906
  57. Rocha, Frederico; Martins, Ricardo; Lourenço, Nuno; Horta, Nuno. "Enhancing a Layout-Aware Synthesis Methodology for Analog ICs by Embedding Statistical Knowledge into the Evolutionary Optimization Kernel". Trabalho apresentado em Doctoral Conference on Computing, Electrical and Industrial Systems, 2013.
    10.1007/978-3-642-37291-9_57
  58. Martins, R.; Lourenco, N.; Horta, N.. "Multi-objective multi-constraint routing of analog ICs using a Modified NSGA-II Approach". Trabalho apresentado em (SMACD), 2012.
    10.1109/SMACD.2012.6339418
  59. Martins, Ricardo; Lourenço, Nuno; Horta, Nuno. "LAYGEN II: automatic analog ICs layout generator based on a template approach". Trabalho apresentado em GECCO '12, 2012.
    10.1145/2330163.2330319
  60. Lourenço, Nuno; Horta, Nuno. "GENOM-POF: multi-objective evolutionary synthesis of analog ICs with corners validation". Trabalho apresentado em GECCO '12, 2012.
    10.1145/2330163.2330318
  61. Martins, R.; Lourenco, N.; Rodrigues, S.; Guilherme, J.; Horta, N.. "AIDA: Automated analog IC design flow from circuit level to layout". Trabalho apresentado em International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2012.
    10.1109/smacd.2012.6339409
  62. Lourenço, Nuno C.; Horta, Nuno C.. "Automatic analog IC layout generation based on a evolutionary computation approach". Trabalho apresentado em GECCO '07, 2007.
    10.1145/1276958.1277396
  63. Lourenço, Nuno. "LAYGEN – Automatic Analog ICs Layout Generator". Trabalho apresentado em 6th Conference on Telecommunications (ConfTele 2007), Peniche, 2007.
  64. Lourenço, N.; Vianello, M.; Guilherme, J.; Horta, N.. "LAYGEN - Automatic layout generation of analog ICs from hierarchical template descriptions". Trabalho apresentado em (PRIME), 2006.
    10.1109/rme.2006.1689934
  65. Lourenco, N.; Horta, N.. "Laygen - An evolutionary approach to automatic analog IC layout generation". Trabalho apresentado em (ICECS), 2005.
    10.1109/icecs.2005.4633414
  66. Lourenço, Nuno. "O Projecto CRESCERE: Raios Cósmicos em Ambiente Escolar Europeu - Uma experiência remota". Trabalho apresentado em XIV Conferência Nacional de Física, Porto, 2005.
    Pessoal de suporte
Artigo em revista
  1. Rafael Vieira; Fabian Näf; Ricardo Martins; Nuno Horta; Nuno Lourenço; Ricardo Póvoa. "A Tunable Gain and Bandwidth Low-Noise Amplifier with 1.44 NEF for EMG and EOG Biopotential Signal". Electronics (2023): https://doi.org/10.3390/electronics12122592.
    10.3390/electronics12122592
  2. Fábio Passos; Nuno Lourenço; Elisenda Roca; Ricardo Martins; Rafael Castro-López; Nuno Horta; Francisco V. Fernández. "PACOSYT: A Passive Component Synthesis Tool Based on Machine Learning and Tailored Modeling Strategies Towards Optimal RF and mm-Wave Circuit Designs". IEEE Journal of Microwaves (2023): https://doi.org/10.1109/JMW.2023.3237260.
    10.1109/JMW.2023.3237260
  3. Gustavo Liñán-Cembrano; Nuno Lourenço; Nuno Horta; José M. de la Rosa. "Design Automation of Analog and Mixed-Signal Circuits Using Neural Networks – A Tutorial Brief". IEEE Transactions on Circuits and Systems II: Express Briefs (2023): https://doi.org/10.1109/TCSII.2023.3323886.
    10.1109/TCSII.2023.3323886
  4. Rafael Vieira; Fábio Passos; Ricardo Martins; Nuno Horta; Nuno Lourenço. "Behavioral Analysis of Noise and Bandwidth Specifications of Heartbeat Detection Circuits for Ultra Low Power Devices". IEEE Access (2023): https://doi.org/10.1109/ACCESS.2023.3255166.
    10.1109/ACCESS.2023.3255166
  5. Ricardo M. F. Martins; Nuno C. C. Lourenço. "Analog Integrated Circuit Routing Techniques: An Extensive Review". IEEE Access (2023): https://doi.org/10.1109/ACCESS.2023.3265481.
    10.1109/ACCESS.2023.3265481
  6. António Gusmão; Pedro Alves; Nuno Horta; Nuno Lourenço; Ricardo Martins. "Differentiable Constraints’ Encoding for Gradient-Based Analog Integrated Circuit Placement Optimization". Electronics (2022): https://doi.org/10.3390/electronics12010110.
    10.3390/electronics12010110
  7. António Gusmão; Rafael Vieira; Nuno Horta; Nuno Lourenço; Ricardo Martins. "Exploiting a Deep Learning Toolbox for Human-Machine Feedback towards Analog Integrated Circuit Placement Automation". Electronics (2022): https://doi.org/10.3390/electronics11233964.
    10.3390/electronics11233964
  8. António Gusmão; Ricardo Póvoa; Nuno Horta; Nuno Lourenço; Ricardo Martins. "DeepPlacer: A custom integrated OpAmp placement tool using deep models". Applied Soft Computing 115 (2022): 108188-108188. https://doi.org/10.1016/j.asoc.2021.108188.
    10.1016/j.asoc.2021.108188
  9. de Gusmão, A.P.L.; Gomes Horta, N.C.; Correia Lourenço, N.C.; Ferreira Martins, R.M.. "Scalable and order invariant analog integrated circuit placement with Attention-based Graph-to-Sequence deep models". Expert Systems with Applications 207 (2022): http://www.scopus.com/inward/record.url?eid=2-s2.0-85132958288&partnerID=MN8TOARS.
    10.1016/j.eswa.2022.117954
  10. Afacan, Engin; Lourenço, Nuno; Martins, Ricardo; Dündar, Günhan. "Review: Machine learning techniques in analog/RF integrated circuit design, synthesis, layout, and test". Integration 77 (2021): 113-130. http://dx.doi.org/10.1016/j.vlsi.2020.11.006.
    10.1016/j.vlsi.2020.11.006
  11. Martins, Ricardo; Lourenço, Nuno; Póvoa, Ricardo; Horta, Nuno. "Shortening the gap between pre- and post-layout analog IC performance by reducing the LDE-induced variations with multi-objective simulated quantum annealing". Engineering Applications of Artificial Intelligence 98 (2021): 104102. http://dx.doi.org/10.1016/j.engappai.2020.104102.
    10.1016/j.engappai.2020.104102
  12. A. Gusmão; Ricardo Filipe Sereno Póvoa; N. Horta; Lourenço, Nuno; R. M. F. Martins. "DeepPlacer: A Custom Analog Integrated Circuit Placement Tool using Deep Models". Applied Soft Computing (2021):
    Em revisão
  13. L. Mendes; J. Vaz; F. Passos; Lourenço, Nuno; R. M. F. Martins; Luis Mendes; Joao Caldinhas Vaz; et al. "In-depth Design Space Exploration of 26.5-to-29.5-GHz 65-nm CMOS Low-Noise Amplifiers for Low-Footprint-and-Power 5G Communications using One-and-Two-Step Design Optimization". IEEE Access 9 (2021): 70353-70368. https://doi.org/10.1109/ACCESS.2021.3078240.
    Acesso aberto • Submetido • 10.1109/ACCESS.2021.3078240
  14. Antonio Canelas; Fabio Passos; Nuno Lourenco; Ricardo Martins; Elisenda Roca; Rafael Castro-Lopez; Nuno Horta; Francisco V. Fernandez. "Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs". IEEE Access 9 (2021): 124152-124164. https://doi.org/10.1109/ACCESS.2021.3110758.
    10.1109/ACCESS.2021.3110758
  15. Póvoa, Ricardo; Canelas, António; Martins, Ricardo; Horta, Nuno; Lourenço, Nuno; Goes, João. "A new family of CMOS inverter-based OTAs for biomedical and healthcare applications". Integration 71 (2020): 38-48. http://dx.doi.org/10.1016/j.vlsi.2019.12.004.
    10.1016/j.vlsi.2019.12.004
  16. Canelas, Antonio; Povoa, Ricardo; Martins, Ricardo; Lourenco, Nuno; Guilherme, Jorge; Carvalho, Joao Paulo; Horta, Nuno; Lourenço, Nuno. "FUZYE: A Fuzzy C-Means Analog IC Yield Optimization using Evolutionary-based Algorithms". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39 1 (2020): 1-13. http://dx.doi.org/10.1109/tcad.2018.2883978.
    10.1109/tcad.2018.2883978
  17. Póvoa, Ricardo; Arya, Richa; Canelas, António; Passos, Fábio; Martins, Ricardo; Lourenço, Nuno; Horta, Nuno. "Sub-µW Tow-Thomas based biquad filter with improved gain for biomedical applications". Microelectronics Journal 95 (2020): 104675. http://dx.doi.org/10.1016/j.mejo.2019.104675.
    10.1016/j.mejo.2019.104675
  18. Fabio Passos; Elisenda Roca; Ricardo Martins; Nuno Lourenco; Saiyd Ahyoune; Javier Sieiro; Rafael Castro-Lopez; Nuno Horta; Francisco V. Fernandez. "Ready-to-Fabricate RF Circuit Synthesis Using a Layout- and Variability-Aware Optimization-Based Methodology". IEEE Access (2020): 1-1. https://doi.org/10.1109/ACCESS.2020.2980211.
    10.1109/ACCESS.2020.2980211
  19. Ricardo Martins; Nuno Lourenco; Nuno Horta; Shenke Zhong; Jun Yin; Pui In Mak; Rui P. Martins. "Design of a 4.2-to-5.1 GHz Ultralow-Power Complementary Class-B/C Hybrid-Mode VCO in 65-nm CMOS Fully Supported by EDA Tools". IEEE Transactions on Circuits and Systems I: Regular Papers (2020): https://doi.org/10.1109/TCSI.2020.3009857.
    10.1109/TCSI.2020.3009857
  20. Martins, Ricardo; Lourenco, Nuno; Passos, Fabio; Povoa, Ricardo; Canelas, Antonio; Roca, Elisenda; Castro-Lopez, Rafael; et al. "Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 38 6 (2019): 989-1002. http://dx.doi.org/10.1109/tcad.2018.2834394.
    10.1109/tcad.2018.2834394
  21. Ricardo Filipe Sereno Póvoa; Nuno Lourenço; Ricardo Martins; António Canelas; Nuno Horta; João Goes. "A Folded Voltage-Combiners Biased Amplifier for Low Voltage and High Energy-Efficiency Applications". IEEE Transactions on Circuits and Systems II: Express Briefs 1 1 (2019): 1-5. http://www.it.pt/Publications/PaperJournal/29412.
    10.1109/TCSII.2019.2913083
  22. Ricardo Martins; Nuno Lourenco; Nuno Horta; Jun Yin; Pui-In Mak; Rui P. Martins. "Many-Objective Sizing Optimization of a Class-C/D VCO for Ultralow-Power IoT and Ultralow-Phase-Noise Cellular Applications". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 1 (2019): 69-82. https://doi.org/10.1109/TVLSI.2018.2872410.
    10.1109/TVLSI.2018.2872410
  23. Povoa, R.; Lourenco, N.; Martins, R.; Canelas, A.; Horta, N.; Goes, J.. "Single-Stage OTA Biased by Voltage-Combiners With Enhanced Performance Using Current Starving". IEEE Transactions on Circuits and Systems II: Express Briefs 65 11 (2018): 1599-1603. http://dx.doi.org/10.1109/tcsii.2017.2777533.
    10.1109/tcsii.2017.2777533
  24. Passos, F.; Martins, R.; Lourenço, N.; Roca, E.; Póvoa, R.; Canelas, A.; Castro-López, R.; Horta, N.; Fernández, F.V.. "Enhanced systematic design of a voltage controlled oscillator using a two-step optimization methodology". Integration 63 (2018): 351-361. http://dx.doi.org/10.1016/j.vlsi.2018.02.005.
    10.1016/j.vlsi.2018.02.005
  25. Povoa, Ricardo; Lourenco, Nuno; Martins, Ricardo; Canelas, Antonio; Horta, Nuno Cavaco Gomes; Goes, Joao. "Single-Stage Amplifier Biased by Voltage Combiners With Gain and Energy-Efficiency Enhancement". IEEE Transactions on Circuits and Systems II: Express Briefs 65 3 (2018): 266-270. http://dx.doi.org/10.1109/tcsii.2017.2686586.
    10.1109/tcsii.2017.2686586
  26. Martins, Ricardo; Lourenço, Nuno; Canelas, António; Horta, Nuno. "Stochastic-based placement template generator for analog IC layout-aware synthesis". Integration 58 (2017): 485-495. http://dx.doi.org/10.1016/j.vlsi.2017.02.012.
    10.1016/j.vlsi.2017.02.012
  27. Pandey, M.; Canelas, A.; Póvoa, R.; Torres, J.A.; Costa Freire, J.; Lourenço, N.; Horta, N.. "Design and application of a CMOS active inductor at Ku band based on a multi-objective optimizer". Integration, the VLSI Journal (2016): http://www.scopus.com/inward/record.url?eid=2-s2.0-84979086215&partnerID=MN8TOARS.
    10.1016/j.vlsi.2016.06.007
  28. Lourenço, N.; Martins, R.; Canelas, A.; Póvoa, R.; Horta, N.. "AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation". Integration, the VLSI Journal (2016): http://www.scopus.com/inward/record.url?eid=2-s2.0-84966648845&partnerID=MN8TOARS.
    10.1016/j.vlsi.2016.04.009
  29. Martins, R.; Póvoa, R.; Lourenço, N.; Horta, N.. "Current-flow and current-density-aware multi-objective optimization of analog IC placement". Integration, the VLSI Journal 55 (2016): 295-306. http://www.scopus.com/inward/record.url?eid=2-s2.0-84992758919&partnerID=MN8TOARS.
    10.1016/j.vlsi.2016.05.008
  30. Martins, R.; Lourenço, N.; Horta, N.. "Multi-objective optimization of analog integrated circuit placement hierarchy in absolute coordinates". Expert Systems with Applications 42 23 (2015): 9137-9151. http://www.scopus.com/inward/record.url?eid=2-s2.0-84940827353&partnerID=MN8TOARS.
    10.1016/j.eswa.2015.08.020
  31. Póvoa, R.; Bastos, I.; Lourenço, N.; Horta, N.. "Automatic synthesis of RF front-end blocks using multi-objective evolutionary techniques". Integration, the VLSI Journal (2015): http://www.scopus.com/inward/record.url?eid=2-s2.0-84942060156&partnerID=MN8TOARS.
    10.1016/j.vlsi.2015.04.005
  32. Lourenço, N.; Canelas, A.; Póvoa, R.; Martins, R.; Horta, N.. "Floorplan-aware analog IC sizing and optimization based on topological constraints". Integration, the VLSI Journal 48 1 (2015): 183-197. http://www.scopus.com/inward/record.url?eid=2-s2.0-84922820131&partnerID=MN8TOARS.
    10.1016/j.vlsi.2014.07.002
  33. Martins, R.; Lourenço, N.; Horta, N.. "Routing analog ICs using a multi-objective multi-constraint evolutionary approach". Analog Integrated Circuits and Signal Processing 78 1 (2014): 123-135. http://www.scopus.com/inward/record.url?eid=2-s2.0-84892669296&partnerID=MN8TOARS.
    10.1007/s10470-013-0088-9
  34. Martins, R.; Lourenço, N.; Canelas, A.; Horta, N.. "Electromigration-aware analog Router with multilayer multiport terminal structures". Integration, the VLSI Journal 47 4 (2014): 532-547. http://www.scopus.com/inward/record.url?eid=2-s2.0-84903315430&partnerID=MN8TOARS.
    10.1016/j.vlsi.2014.02.003
  35. Martins, R.; Lourenço, N.; Horta, N.. "LAYGEN II-automatic layout generation of analog integrated circuits". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 32 11 (2013): 1641-1654. http://www.scopus.com/inward/record.url?eid=2-s2.0-84886665180&partnerID=MN8TOARS.
    10.1109/TCAD.2013.2269050
Capítulo de livro
  1. João L. C. P. Domingues; Pedro J. C. D. C. Vaz; António P. L. Gusmão; Nuno C. G. Horta; Nuno C. C. Lourenço; Ricardo M. F. Martins. "Introduction". 2023.
    10.1007/978-3-031-25099-6_1
  2. João L. C. P. Domingues; Pedro J. C. D. C. Vaz; António P. L. Gusmão; Nuno C. G. Horta; Nuno C. C. Lourenço; Ricardo M. F. Martins. "Convergence Classifier and Frequency Guess Predictor Based on ANNs". 2023.
    10.1007/978-3-031-25099-6_3
  3. João L. C. P. Domingues; Pedro J. C. D. C. Vaz; António P. L. Gusmão; Nuno C. G. Horta; Nuno C. C. Lourenço; Ricardo M. F. Martins. "Process, Voltage and Temperature Corner Performance Estimator Using ANNs". 2023.
    10.1007/978-3-031-25099-6_4
  4. João L. C. P. Domingues; Pedro J. C. D. C. Vaz; António P. L. Gusmão; Nuno C. G. Horta; Nuno C. C. Lourenço; Ricardo M. F. Martins. "Background and Related Work". 2023.
    10.1007/978-3-031-25099-6_2
  5. Rafael Vieira; Nuno Horta; Nuno Lourenço; Ricardo Póvoa. "Background and State-of-the-Art". 2021.
    10.1007/978-3-030-70887-0_2
  6. Rafael Vieira; Nuno Horta; Nuno Lourenço; Ricardo Póvoa. "Proposed Design and Implementation". 2021.
    10.1007/978-3-030-70887-0_3
  7. Rafael Vieira; Nuno Horta; Nuno Lourenço; Ricardo Póvoa. "Layout". 2021.
    10.1007/978-3-030-70887-0_4
  8. Rafael Vieira; Nuno Horta; Nuno Lourenço; Ricardo Póvoa. "Conclusions and Future Work". 2021.
    10.1007/978-3-030-70887-0_5
  9. Rafael Vieira; Nuno Horta; Nuno Lourenço; Ricardo Póvoa. "Introduction". 2021.
    10.1007/978-3-030-70887-0_1
  10. António Gusmão; Nuno Horta; Nuno Lourenço; Ricardo Martins. "Artificial Neural Network Overview". 2020.
    10.1007/978-3-030-50061-0_2
  11. António Gusmão; Nuno Horta; Nuno Lourenço; Ricardo Martins. "State-of-the-Art in Analog Integrated Circuit Placement". 2020.
    10.1007/978-3-030-50061-0_3
  12. António Gusmão; Nuno Horta; Nuno Lourenço; Ricardo Martins. "ANN Models for Analog Placement Automation". 2020.
    10.1007/978-3-030-50061-0_4
  13. Rosa, J.P.S.; Guerra, D.J.D.; Horta, N.C.G.; Martins, R.M.F.; Lourenço, N.C.C.. "Using ANNs to Size Analog Integrated Circuits". 45-66. 2020.
    10.1007/978-3-030-35743-6_4
  14. Rosa, J.P.S.; Guerra, D.J.D.; Horta, N.C.G.; Martins, R.M.F.; Lourenço, N.C.C.. "Overview of Artificial Neural Networks". 21-44. 2020.
    10.1007/978-3-030-35743-6_3
  15. Rosa, J.P.S.; Guerra, D.J.D.; Horta, N.C.G.; Martins, R.M.F.; Lourenço, N.C.C.. "ANNs as an Alternative for Automatic Analog IC Placement". 67-101. 2020.
    10.1007/978-3-030-35743-6_5
  16. Gusmão, A.; Horta, N.; Lourenço, N.; Martins, R.. "Analog IC placement generation via neural networks from unlabeled data". 1-87. 2020.
  17. António Gusmão; Nuno Horta; Nuno Lourenço; Ricardo Martins. "Introduction". 2020.
    10.1007/978-3-030-50061-0_1
  18. António Gusmão; Nuno Horta; Nuno Lourenço; Ricardo Martins. "Conclusions and Future Work". 2020.
    10.1007/978-3-030-50061-0_6
  19. António Gusmão; Nuno Horta; Nuno Lourenço; Ricardo Martins. "Results". 2020.
    10.1007/978-3-030-50061-0_5
  20. Rosa, J.P.S.; Guerra, D.J.D.; Horta, N.C.G.; Martins, R.M.F.; Lourenço, N.C.C.. "Related Work". 9-20. 2020.
    10.1007/978-3-030-35743-6_2
  21. Lourenço, R.; Lourenço, N.; Horta, N.. "Conclusion and future work". 63-64. 2015.
    10.1007/978-3-319-15955-3_7
  22. Lourenço, R.; Lourenço, N.; Horta, N.. "Previous works on automated analog IC sizing". 7-16. 2015.
    10.1007/978-3-319-15955-3_2
  23. Lourenço, R.; Lourenço, N.; Horta, N.. "Multi-objective framework implementation". 33-41. 2015.
    10.1007/978-3-319-15955-3_4
  24. Lourenço, R.; Lourenço, N.; Horta, N.. "AIDA-CMK: AIDA-C with MOO framework". 17-31. 2015.
    10.1007/978-3-319-15955-3_3
  25. Lourenço, R.; Lourenço, N.; Horta, N.. "Results for analog IC design". 51-61. 2015.
    10.1007/978-3-319-15955-3_6
  26. Lourenço, R.; Lourenço, N.; Horta, N.. "Kernel validation using CEC2009 benchmarks". 43-49. 2015.
    10.1007/978-3-319-15955-3_5
  27. Póvoa, Ricardo; Lourenço, Ricardo; Lourenço, Nuno; Canelas, António; Martins, Ricardo; Horta, Nuno. "Synthesis of LC-Oscillators Using Rival Multi-Objective Multi-Constraint Optimization Kernels". In Performance Optimization Techniques in Analog, Mixed-Signal, and Radio-Frequency Circuit Design, 1-27. IGI Global, 2014.
    10.4018/978-1-4666-6627-6.ch001
  28. Canelas, António; Martins, Ricardo; Póvoa, Ricardo; Lourenço, Nuno; Guilherme, Jorge; Horta, Nuno. "Enhancing an Automatic Analog IC Design Flow by Using a Technology-Independent Module Generator". In Performance Optimization Techniques in Analog, Mixed-Signal, and Radio-Frequency Circuit Design, 102-133. IGI Global, 2014.
    10.4018/978-1-4666-6627-6.ch005
  29. Rocha, F.A.E.; Martins, R.M.F.; Lourenço, N.C.C.; Horta, N.C.G.. "State-of-the-art on automatic analog IC sizing". 7-22. 2014.
    10.1007/978-3-319-02189-8_2
  30. Rocha, F.A.E.; Martins, R.M.F.; Lourenço, N.C.C.; Horta, N.C.G.. "Conclusions and future work". 67-69. 2014.
    10.1007/978-3-319-02189-8_6
  31. Lourenço, Nuno; Martins, Ricardo; Barros, Manuel; Horta, Nuno. "Analog Circuit Design Based on Robust POFs Using an Enhanced MOEA with SVM Models". In Analog/RF and Mixed-Signal Circuit Systematic Design, 149-167. Springer Berlin Heidelberg, 2013.
    10.1007/978-3-642-36329-0_7
  32. Martins, R.M.F.; Lourenço, N.C.C.; Horta, N.C.G.. "Conclusions and future work". 95-98. 2013.
    10.1007/978-3-642-33146-6_7
Edição de número de revista
  1. Martins, Ricardo; Lourenço, Nuno; Fábio Moreira de Passos. "Special Issue on Advanced Design Techniques and EDA Methodologies for Analog, RF, and mm-Wave Circuit Design". Electronics MDPI (2023):
    Publicado
Livro
  1. João L. C. P. Domingues; Pedro J. C. D. C. Vaz; António P. L. Gusmão; Nuno C. G. Horta; Nuno C. C. Lourenço; Ricardo M. F. Martins. Speeding-Up Radio-Frequency Integrated Circuit Sizing with Neural Networks. 2023.
    10.1007/978-3-031-25099-6
  2. Rafael Vieira; Nuno Horta; Nuno Lourenço; Ricardo Póvoa. Tunable Low-Power Low-Noise Amplifier for Healthcare Applications. 2021.
    10.1007/978-3-030-70887-0
  3. Vieira, R.; Horta, N.; Lourenço, N.; Póvoa, R.. Preface. 2021.
  4. Rosa, João P. S.; Guerra, Daniel J. D.; Horta, Nuno C. G.; Martins, Ricardo M. F.; Lourenço, Nuno C. C.. Using Artificial Neural Networks for Analog Integrated Circuit Design Automation. Springer International Publishing. 2020.
    10.1007/978-3-030-35743-6
  5. Gusmão, António; Horta, Nuno; Lourenço, Nuno; Martins, Ricardo; Gusmão, António; Nuno Horta; Lourenço, Nuno; Martins, Ricardo. Analog IC Placement Generation via Neural Networks from Unlabeled Data. Springer International Publishing. 2020.
    Aceite para publicação • 10.1007/978-3-030-50061-0
  6. Lourenço, Nuno; Martins, Ricardo; Horta, Nuno. Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects. Springer International Publishing. 2017.
    10.1007/978-3-319-42037-0
  7. Martins, Ricardo; Lourenço, Nuno; Horta, Nuno. Analog Integrated Circuit Design Automation. Springer International Publishing. 2017.
    10.1007/978-3-319-34060-9
  8. Lourenço, Ricardo; Lourenço, Nuno; Horta, Nuno. AIDA-CMK: Multi-Algorithm Optimization Kernel Applied to Analog IC Sizing. Springer International Publishing. 2015.
    10.1007/978-3-319-15955-3
  9. Rocha, Frederico A.E.; Martins, Ricardo M.F.; Lourenço, Nuno C.C.; Horta, Nuno C.G.. Electronic Design Automation of Analog ICs combining Gradient Models with Multi-Objective Evolutionary Algorithms. Springer International Publishing. 2014.
    10.1007/978-3-319-02189-8
  10. Martins, Ricardo M. F.; Lourenço, Nuno C. C.; Horta, Nuno C. G.. Generating Analog IC Layouts with LAYGEN II. Springer Berlin Heidelberg. 2013.
    10.1007/978-3-642-33146-6
Resumo em conferência
  1. Fábio Passos; Lourenço, Nuno; Luís Miguel Moreira Mendes; Martins, Ricardo; Caldinhas Vaz, João; Nuno Horta. "A 23.5-32.5GHz, 17dBm PSAT and 37.5%PAE Power Amplifier Fully Synthesized Using an Automated Design Methodology Aided by ML Passive Component Models". Trabalho apresentado em International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuit Design (SMACD), 2023.
    Aceite para publicação
Tese / Dissertação
  1. Lourenço, Nuno. "Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects". Doutoramento, Universidade de Lisboa Instituto Superior Técnico, 2014.
  2. Lourenço, Nuno. "Automatic Layout Generation of Analog ICs based on Hierarchical Template Descriptions and Intelligent Computing Techniques". Mestrado, Universidade de Lisboa Instituto Superior Técnico, 2007.
  3. Lourenço, Nuno. "Automatic Analog IC Layout Generator". Licenciatura, Universidade de Lisboa Instituto Superior Técnico, 2005.
Website
  1. Lourenço, Nuno. AIDAsoft Analog IC Design Automation. 2015. http://aidasoft.com/.

Propriedade Intelectual

Patente
  1. Jose Teixeira De Sousa; N. Lourenço; Victor Manuel Goncalves Martins; Alexandre Miguel Dias Santos; Nelson Goncalo do Rosario Ribeiro. 2012. "Reconfigurable coprocessor architecture template for nested loops and programming tool". Estados Unidos.
    Concedida/Emitida
  2. José Teixeira de Sousa; N. Lourenço; Nelson Goncalo do Rosario Ribeiro; Victor Manuel Goncalves Martins; Ricardo Jorge Santos Martins. 2011. "Network core access architecture". Estados Unidos.
    Expirada

Outros

Outra produção
  1. TSMC65nm Integrated Circuit Prototype. Europractice TSMC 65nm CMOS LPMS/RF run 9170. mmWave LNA. 2022. Nuno Lourenço.
  2. UMC 110nm Integrated Circuit Prototype. Europractice UMC 110nm. LNA for EMG and EOG, Fully Integrated Inductive DCDC converter. 2021. Nuno Lourenço; Pedro Santos; Rafael Vieira; Ricardo Martins; Ricardo Povoa.
  3. Integrated Circuit Prototype. MOSIS TSMC 65GP. 4-6GHz VCO. 2019. Nuno Lourenço.
  4. UMC0.13µm Integrated Circuit Prototype. Europractice’s UMC L13078237/A12310/01. 2018. Nuno Lourenço.
  5. UMC0.13µm Integrated Circuit Prototype. Europractice UMC L13077894/R14120/01.. 2017. Ricardo Povoa; Nuno Lourenço.
  6. AMS0.35µm Integrated Circuit Prototype. Europractice AMS 0.35µm.. 2017. Fábio Passos; Nuno Lourenço; Martins, Ricardo.
  7. UMC0.13µm Integrated Circuit Prototype. Europractice UMC L13077146/R14120/02. 2016. Ricardo Povoa; Nuno Lourenço; Ricardo Martins.
  8. UMC0.13µm Integrated Circuit Prototype. Europractice UMC L13076714/A12310/01.. VC OTA. 2015. Ricardo Povoa; Nuno Lourenço.
Atividades

Apresentação oral de trabalho

Título da apresentação Nome do evento
Anfitrião (Local do evento)
2019/07 Artificial Neural Networks as an Alternative for Automatic Analog IC Placement International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)
(Lausanne, Suiça)
2019/07 Layout-Aware Sizing of Analog ICs using Floorplan & Routing Estimates for Parasitic Extraction International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)
(Lausanne, Suiça)
2018/07 A 20 dB Gain Two-Stage Low-Noise Amplifier with High Yield for 5 GHz Applications International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)
(Prague, República Checa)
2018/07 On the Exploration of Promising Analog IC Designs via Artificial Neural Networks International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)
(Prague, República Checa)
2018/03 Enhanced Analog and RF IC Sizing Methodology using PCA and NSGA-II Optimization Kernel Design, Automation & Test in Europe Conference (DATE
(Dresden, Alemanha)
2018 Systematic Analog IC Design and Reuse AIDASoft tutorial
Thales Alenia Space (Toulouse, França)
2016/06 Automated analog IC design constraints generation for a layout-aware sizing approach International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)
(Lisboa, Portugal)
2015/10 Effective use of optimization tools for Integrated Circuits Sizing Tutorial
Thales Alenia Space (Toulouse, França)
2015/06 Analog IC Design Automation: Approaches and Challenges Tutorial
IEEE International Symposium on Circuits and Systems (ISCAS) (Lisboa, Portugal)
2015/03 AIDA-C: Layout-Aware Analog IC Synthesis and Optimization University Booth - Design, Automation and Test in Europe Conference
(Grenoble, França)
2015/03 Layout-Aware Synthesis of Analog ICs using Flooplan & Routing Estimates for Parasitic Extraction Design, Automation & Test in Europe Conference (DATE)
(Grenoble, França)
2014/04 AIDA: Analog Integrated Circuits Design Automation Exhibition - 23rd Workshop on Advances in Analog Circuit Design
(Lisboa, Portugal)
2014/03 AIDA: Analog Integrated Circuits Design Automation University Booth - Design, Automation and Test in Europe Conference
(Dresden, Alemanha)
2014/03 AIDA-C: Analog Integrated Circuits Synthesis and Optimization Tutorial
Thales Alenia Space (Toulouse, França)
2013/04 Enhancing a Layout-aware Synthesis Methodology for Analog ICs by Embedding Statistical Knowledge into the Evolutionary Optimization Kernel Doctoral Conference on Computing, Electrical and Industrial Systems
(Caparica, Portugal)
2012/09 AIDA: Automated Analog IC Design Flow from Circuit Level to Layout International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)
(Sevilha, Espanha)
2012/07 GENOM-POF: Multi-Objective Evolutionary Synthesis of Analog ICs with Corners Validation Genetic and Evolutionary Computation Conference (GECCO)
Philadelphia (Estados Unidos)
2012/07 GENOM-POF: Multi-Objective Evolutionary Synthesis of Analog ICs with Corners Validation "HUMIES” Awards for Human-Competitive Results
2010/09 Coreworks’ technology exhibited at Xilinx booth Exhibition- International Broadcasting Convention (IBC)
(Amsterdam, Países Baixos)
2008/02 Coreworks’ technology Exhibition - DesignCon 2008
(San Jose, CA, Estados Unidos)
2007/07 LAYGEN – Automatic Analog ICs Layout Generator 6th Conference on Telecommunications (ConfTele 2007)
(Peniche, Portugal)
2006/06 LAYGEN Automatic Layout Generation of Analog ICs from Hierarchical Template Descriptions IEEE Conference on PhD Research in Microelectronics and Electronics (PRIME)
(Lecce)

Orientação

Título / Tema
Papel desempenhado 		Curso (Tipo)
Instituição / Organização
2024/02/29 - Atual Generative AI Solutions for Analog Integrated Circuits Design
Orientador
 Engenharia Electrotécnica e de Computadores (Doutoramento)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2024/02 - Atual Agents that Design Circuits: Reinforcement Learning approach to Analog Integrated Circuit Design Automation
Orientador
 Engenharia Eletrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2024/02 - Atual Experimental Kit for introducing electronics and computer engineering to young children (8 – 12 year old)
Orientador
 Ciências de Engenharia - Engenharia de Redes de Comunicações (Licenciatura/Bacharelato)
Universidade de Lisboa Instituto Superior Técnico Campus Taguspark, Portugal
2024/02 - Atual Assisting Interconnects’ Drawing with Predictive Machine/Deep Learning
Orientador
 Engenharia de Telecomunicações e Informática (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2024/02 - Atual Generator for a gain-boosted folded cascode Operational Transconductance Amplifier (OTA)
Orientador
 Engenharia Eletrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2023/09 - Atual Generative Artificial Intelligence for Analog Integrated Circuit Design Automation
Orientador
 Engenharia Electrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2023/09 - Atual Ensemble Machine/Deep Learning for Performance Prediction
Orientador
 Engenharia Eletrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2020/09/01 - Atual A Tunable Front-End Receiver IC with High Energy-Efficiency for Biomedical Applications and Healthcare
Orientador
 Engenharia Electrotécnica e de Computadores (Doutoramento)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2020/03/01 - Atual Deep Learning Techniques for End-to-end Deep Nanometer Analog and Radio Frequency Integrated Circuit Design Automation
Orientador
 Engenharia Electrotécnica e de Computadores (Doutoramento)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2022/02/13 - 2022/11/10 Deep Neural Networks for Behavioral Modeling of Analog ICs
Orientador
 Engenharia Eletrotécnica e de Computadores
Universidade de Lisboa Instituto Superior Técnico, Portugal
2022/02/10 - 2022/11 Deep Reinforcement Learning applied to Analog Integrated Circuit Sizing
Orientador
 Engenharia Eletrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2018/10/01 - 2019/12/19 Semi-Supervised Artificial Neural Networks towards Push-Button Analog IC Placement
Orientador
 Engenharia Electrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2018/06/01 - 2019/01/14 On the Exploration of Automatic Analog Integrated Circuit Placement using Neural Networks
Orientador
 Engenharia Electrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2017/07/07 - 2018/10/01 EDA to the cloud – a case study to increase both effectiveness and user experience of EDA tools
Orientador
 Engenharia Electrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2017/10/01 - 2018/07/12 Using Artificial Neural Networks to Size Analog Integrated Circuits
Orientador
 Engenharia Electrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2017/10/01 - 2018/01/23 Enhancing Analog and RF IC Sizing Methodology using PCA and NSGA-II Optimization Kernel
Orientador
 Engenharia Electrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2016/02/01 - 2016/11/13 E-Conf: A Conference Management System
Orientador
 Engenharia Electrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2015/10/01 - 2016/07/11 AIDA-C: Evolutionary Optimization Techniques applied to Analog IC Design
Orientador
 Engenharia Electrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2015/02/01 - 2015/11/24 Parallel Computing applied to Analog IC Layout-Aware Sizing and Optimization
Orientador
 Engenharia Electrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal

Organização de evento

Nome do evento
Tipo de evento (Tipo de participação) 		Instituição / Organização
2021/10/01 - 2022/07/20 General Chair for IEEE SMACD 2022 (2022/06/12 - 2022/06/15)
Conferência (Presidente da Comissão Organizadora)
 Instituto de Telecomunicações, Portugal
2019 - 2021 SMACD 2021 Publication Chair (2021 - 2021)
Conferência (Membro da Comissão Organizadora)
 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2021, Alemanha
2019 - 2021 Organizer of Special Session: Machine Learning for Mixed-Signal EDA: Enabling Design Engineers with Learning Tools and Algorithms" (2021 - 2021)
Conferência (Outra)
 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2021, Alemanha
2020 - 2020 PRIME 2020 Technical Program Committee (2020 - 2020)
Conferência (Membro da Comissão Científica)
 Conference on PhD Research in Microelectronics and Electronics (PRIME) 2021, Alemanha
2019 - 2020 SMACD 2020 Technical Program Committee (2020 - 2020)
Conferência (Membro da Comissão Científica)
 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2021, Alemanha
2018 - 2019 Organizer of Special Session “Deep Learning for Analog EDA: Are we there yet?” (2019/07/15 - 2019/07/18)
Conferência (Outra)
 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2019, Suiça
2018 - 2019 SMACD 2019 Publication Chair (2019/07/15 - 2019/07/18)
Conferência (Membro da Comissão Organizadora)
 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2019, Suiça
2018 - 2019 PRIME 2019 Technical Program Committee (2019/07/15 - 2019/07/18)
Conferência (Membro da Comissão Científica)
 Conference on PhD Research in Microelectronics and Electronics (PRIME) 2019, Suiça
2018 - 2019 PRIME 2019 Publication Chair (2019/07/15 - 2019/07/18)
Conferência (Membro da Comissão Organizadora)
 Conference on PhD Research in Microelectronics and Electronics (PRIME) 2019, Suiça
2018 - 2018 SMACD 2019 Technical Program Committee (2019/07/15 - 2019/07/18)
Conferência (Membro da Comissão Científica)
 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2019, Suiça
2017 - 2018 SMACD 2018 Technical Program Committee (2018/07/02 - 2018/07/05)
Conferência (Membro da Comissão Científica)
 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2018, República Checa
2017 - 2018 PRIME 2018 Technical Program Committee (2018/07/02 - 2018/07/05)
Conferência (Membro da Comissão Científica)
 Conference on PhD Research in Microelectronics and Electronics (PRIME) 2018, República Checa
2017 - 2018 Organizer of Special Session “New Solutions for Analog and Radio-Frequency Layout Synthesis” (2018/07/02 - 2018/07/05)
Conferência (Outra)
 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2018, República Checa
2016 - 2017 SMACD 2017 Technical Program Committee (2017/06/12 - 2017/06/15)
Conferência (Membro da Comissão Científica)
 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2017, Itália
2016 - 2017 SMACD 2017 Publication Chair (2017/06/12 - 2017/06/15)
Conferência (Membro da Comissão Organizadora)
 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2017, Itália
2016 - 2017 PRIME 2017 Technical Program Committee (2017/06/12 - 2017/06/15)
Conferência (Membro da Comissão Científica)
 Conference on PhD Research in Microelectronics and Electronics (PRIME) 2017, Itália
2015 - 2016 PRIME 2016 Publication Chair (2016/06/12 - 2016/06/15)
Conferência (Membro da Comissão Organizadora)
 IEEE Conference on PhD Research in Microelectronics and Electronics (PRIME) 2016, Portugal
2015 - 2016 SMACD 2016 Technical Program Committee (2016/06/27 - 2016/06/30)
Conferência (Membro da Comissão Científica)
 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2016, Portugal
2015 - 2016 SMACD 2016 Publication Chair (2016/06/27 - 2016/06/30)
Conferência (Membro da Comissão Organizadora)
 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2016, Portugal
2015 - 2016 PRIME 2016 Technical Program Committee (2016/06/27 - 2016/06/30)
Conferência (Membro da Comissão Científica)
2015 - 2015 ISCAS 2015 Volunteer (2015/05/24 - 2015/05/27)
Conferência (Membro da Comissão Organizadora)
 IEEE International Symposium on Circuits and Systems (ISCAS) 2015, Portugal
2014 - 2014 23rd AACD Volunteer (2014/04/08 - 2014/04/10)
Oficina (workshop) (Membro da Comissão Organizadora)
 23rd Workshop on Advances in Analog Circuit Design, Portugal

Júri de grau académico

Tema
Tipo de participação 		Nome do candidato (Tipo de grau)
Instituição / Organização
2022/12/14 Computational Methods for Automatic Analog Integrated Circuit Design
Arguente principal
 Konstantinos Touloupas (Doutoramento)
National Technical University of Athens School of Electrical and Computer Engineering, Grécia
2022 Applying Data-Mining and Clustering Techniques to Portfolio Composition
Arguente principal
 Miguel Henrique Vaz Viegas (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2022 Portfolio Selection and Trading Model based on Genetic Algorithms, K-Means Clustering, Fundamental Indicators and Technical Indicators
Arguente principal
 João Quinas Guterres (Mestrado)
2022 Deep Reinforcement Learning applied to Analog Integrated Circuit Sizing
Orientador
 Tomás Bessa de Curado (Mestrado)
2022 Deep Neural Networks for Behavioral Modeling of Analog ICs
Orientador
 André Carneiro Amaral (Mestrado)
2018/06 Routing Heuristics in LTE-Advanced Networks
Vogal
 Bruno Alexandre Moreira Pincho (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2018/06 Using Artificial Neural Networks to Size Analog Integrated Circuits
Orientador
 João Pedro da Silva Rosa (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2018/06 EDA to the cloud – a case study to increase both effectiveness and user experience of EDA tools.
Orientador
 Pedro Baptista Sacadura Biscaia (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2017/11 Enhanced Analog and RF IC Sizing Methodology using PCA and NSGA-II Optimization Kernel
Orientador
 Tiago Claro Oliveira Miranda Pessoa (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2016/05 AIDA-C: Evolutionary Optimization Techniques applied to Analog IC Design
Orientador
 André Ricardo Henriques Ferreira (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2015 Parallel Computing applied to Analog IC Layout-Aware Sizing and Optimization
Orientador
 David José Rodrigues Neves (Mestrado)

Arbitragem científica em conferência

Nome da conferência Local da conferência
2016 - 2021 Conference on PhD Research in Microelectronics and Electronics Several Editions
2016 - 2021 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design Several Editions
2015 - 2021 IEEE International Symposium on Circuits and Systems (ISCAS) Several Editions
2017 - 2017 New Generation of Circuits and Systems Conference (NGCAS) Genova, Italy
2015 - 2015 IEEE Computer Society Annual Symposium in VLSI (ISVLSI) Montpellier, France

Arbitragem científica em revista

Nome da revista (ISSN) Editora
2022/04/01 - Atual Associate Editor - Integration Elsivier
2022/02/01 - Atual Guest Editor - Electronics SI "Advanced Design Techniques and EDA Methodologies for Analog, RF and MM-Wave Circuit Design" MDPI
2020 - Atual IEEE Transactions on Circuits and Systems (1558-0806) IEEE
2020 - Atual Expert Systems with Applications (0957-4174) Elsevier
2020 - Atual Journal of Low Power Electronics and Applications (2079-9268) MDPI
2019 - Atual Computers and Electrical Engineering (0045-7906) Elsevier
2019 - Atual IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems IEEE
2018 - Atual AEÜ - International Journal of Electronics and Communications (1434-8411) Elsevier
2018 - Atual Karbala International Journal of Modern Science (2405-6103) Elsevier
2017 - Atual Information Sciences (0020-0255) Elsevier
2017 - Atual Journal of Computational Science (1877-7503) Elsevier
2016 - Atual Integration (0167-9260) Elsevier
2015 - Atual Microelectronics Journal (0026-2692) Elsivier

Curso / Disciplina lecionado

Disciplina Curso (Tipo) Instituição / Organização
2023/09 - Atual Eletrónica dos Sistemas Embebidos Ciências de Engenharia - Engenharia Eletrónica (Licenciatura) Universidade de Lisboa Instituto Superior Técnico Campus Taguspark, Portugal
2022/02/15 - 2023/07/20 Programação 2 Engenharia Informática Universidade de Évora Escola de Ciências e Tecnologia, Portugal
2022/09/13 - 2023/02/07 Tópicos de Ferramentas Numéricas Engenharia Informática (Licenciatura) Universidade de Évora Escola de Ciências e Tecnologia, Portugal
2021/09/13 - 2022/02/13 Programação I (Licenciatura) Universidade de Évora Departamento de Informática, Portugal
2015 - 2019 Digital Systems Ciências de Engenharia - Engenharia Aeroespacial (Licenciatura) Universidade de Lisboa Instituto Superior Técnico, Portugal
2015 - 2018 Digital Systems Ciências de Engenharia - Engenharia Electrotécnica e de Computadores (Mestrado integrado) Universidade de Lisboa Instituto Superior Técnico, Portugal
2015 - 2016 Algorithms and Data Structures Ciências de Engenharia - Engenharia Electrotécnica e de Computadores (Licenciatura) Universidade de Lisboa Instituto Superior Técnico, Portugal
2015/02/07 - 2015/07/20 Object Oriented Programming Engenharia Electrotécnica e de Computadores (Mestrado integrado) Universidade de Lisboa Instituto Superior Técnico, Portugal
2005/08 - 2006/08 Digital Systems Ciências de Engenharia - Engenharia Electrotécnica e de Computadores (Licenciatura) Universidade de Lisboa Instituto Superior Técnico, Portugal

Membro de associação

Nome da associação Tipo de participação
2014/01/01 - Atual Institute of Electrical and Electronics Engineers (IEEE) Member

Membro de comissão

Descrição da atividade
Tipo de participação 		Instituição / Organização
2022/06/15 - Atual SMACD Steering Committee
Membro

Outro júri / avaliação

Descrição da atividade Instituição / Organização
2019/06/01 - 2019/10/31 Project review for public funding agency. Grantová agentura Ceské republiky, República Checa
Distinções

Prémio

2019 Best Paper Award 2019 - Integration, the VLSI journal
Integration, the VLSI Journal - Elsevier, Países Baixos
2018 Best Paper Award (SMACD 2018)
International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2018, República Checa
2016 Best Paper Award (SMACD 2016)
International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2016, Portugal
2015 Winner of the Design Automation Competition (SMACD 2015)
International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2015, Turquia
2015 Silver Leaf Best Paper Award at IEEE PRIME 2015
Conference on PhD Research in Microelectronics and Electronics Committee, Reino Unido
2010 DesignVision Award on the category of Semiconductor IP
International Engineering Consortium, Estados Unidos

Outra distinção

2019 Best Paper Award Runner-Up (SMACD 2019)
International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2019, Suiça
2018 IST Outstanding Teaching Award
Universidade de Lisboa Instituto Superior Técnico, Portugal
2017 Best Paper Award Nominee (SMACD 2017)
International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2017, Itália
2016 IST Outstanding Teaching Award
Universidade de Lisboa Instituto Superior Técnico, Portugal
2015 Nominee for Best Student Paper Award - ISCAS 2015
IEEE International Symposium on Circuits and Systems (ISCAS) 2015, Portugal
2014 Best Student Paper Award Runner-Up - ISCAS 2014
IEEE International Symposium on Circuits and Systems (ISCAS) 2014, Austrália
2012 Honourable Mention on Design Automation Competition - SMACD 2012
International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design Committee (SMACD) 2012, Espanha
2012 Finalist of the GECCO "Humies Competition"
Genetic and Evolutionary Computation Conference (GECCO) 2012, Estados Unidos