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Ricardo Chaves. Completed his PhD in Computer Engenering in 2007 at Technische Universiteit Delft and Universidade de Lisboa, Instituto Superior Técnico. Is an Associate Professor at Universidade de Lisboa and Researcher in Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa. Published 38 articles in journals and 6 sections in books. Organized 3 event(s). Supervised 1 PhD thesis(es). Has received 1 awards and/or honors. Participates as Principal investigator in 1 project and Researcher in 11 projects. Works in the areas of cryptography systems, reconfigurable hardware architectures, and on embedded and user oriented systems.. In his curriculum Ciência Vitae the most frequent terms in the context of scientific, technological and artistic-cultural output are: Cyber-Security; Internet of Things; Location Proofs; Digital Certificates; Heterogeneous Systems; Bioinformatics; Energy Efficiency; Performance Modeling; Heterogeneous Architecture with Multiple Cores; Analysis of Biological Sequences; High Speed Sequencing Technologies; Parallel Algorithms.
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Identification

Personal identification

Full name
Ricardo Chaves

Citation names

  • Chaves, Ricardo

Author identifiers

Ciência ID
1111-7630-8E85
ORCID iD
0000-0002-4450-3983

Knowledge fields

  • Engineering and Technology - Electrotechnical Engineering, Electronics and Informatics - Computer Hardware and Architecture

Languages

Language Speaking Reading Writing Listening Peer-review
English Proficiency (C2) Proficiency (C2) Advanced (C1) Proficiency (C2)
French Beginner (A1) Beginner (A1) Beginner (A1) Beginner (A1)
Portuguese Proficiency (C2) Proficiency (C2) Proficiency (C2) Proficiency (C2)
Spanish; Castilian Intermediate (B1) Intermediate (B1) Beginner (A1) Intermediate (B1)
Education
Degree Classification
2007/12/11
Concluded
 Computer Engenering (Doutoramento)
Technische Universiteit Delft, Netherlands
2007
Concluded
 Engenharia Electrotécnica e de Computadores (Doutoramento)
Universidade de Lisboa Instituto Superior Técnico, Portugal
"Secure Computing on Reconfigurable Devices" (THESIS/DISSERTATION)
 n.a.
2003
Concluded
 Engenharia Electrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
"RDSP: Processador Digital de Sinal com Suporte para Aritmética por Resíduos" (THESIS/DISSERTATION)
 n.a.
2001
Concluded
 Engenharia Electrotécnica e de Computadores (Licenciatura)
Universidade de Lisboa Instituto Superior Técnico, Portugal
 15
Affiliation

Science

Category
Host institution 		Employer
2008/01/01 - Current Researcher (Research) Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
2007/12/21 - 2008/08/24 Contracted Researcher (Research) Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal

Teaching in Higher Education

Category
Host institution 		Employer
2017 - Current Associate Professor (University Teacher) Universidade de Lisboa, Portugal
2016 - 2017 Assistant Professor (University Teacher) Universidade de Lisboa, Portugal
2015 - 2017 Assistant Professor (University Teacher) Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
2008/09/01 - 2016/12/20 Assistant (University Teacher) Universidade de Lisboa Instituto Superior Técnico, Portugal
2013 - 2016 Assistant Professor (University Teacher) Universidade de Lisboa Instituto Superior Técnico, Portugal
Projects

Grant

Designation Funders
2023/09/01 - 2027/04/02 QUANTUM SECURE NETWORKS PARTNERSHIP (QSNP)
HORIZON-CL4-2021-DIGITAL-EMERGING-02-19, Project nº 101080116,
Researcher
Ongoing
2023/11/01 - 2027/02/01 NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLiscon photonicS (NEUROPULS)
HORIZON-CL4-2021-DIGITAL-EMERGING-01-01
Researcher
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
2021/12/01 - 2024/05/31 Disruptive SDN secure communications for European Defence
EDIDP-CSAMN-SDN-202-74-DISCRETION
Researcher
Universidade de Lisboa Instituto Superior Técnico, Portugal
Ongoing
2018 - 2021/11 SGA1 (Specific Grant Agreement 1) OF THE EUROPEAN PROCESSOR INITIATIVE (EPI)
826647
Researcher
European Commission
Concluded
2012/03 - 2015/08 THREadS: Multitask System Framework with Transparent Hardware Reconfiguration
Provided by PTCRIS: 117329
Researcher
Fundação para a Ciência e a Tecnologia
2011/01 - 2013/12 HELIX: Heterogeneous Multi-Core Architecture for Biological Sequence Analysis
Provided by PTCRIS: 113999
 Fundação para a Ciência e a Tecnologia

Contract

Designation Funders
2018/10/01 - 2021/09/30 SureThing: Certificação de localização de dispositivos para a Internet das Coisas
PTDC/CCI-COM/31440/2017
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia
Concluded
2018/06/01 - 2021/05/31 Processamento de Elevado Desempenho e Energeticamente Eficiente para Aplicações de Bioinformática nos Sistemas Heterogéneos Emergentes
PTDC/CCI-COM/31901/2017
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia
Concluded
2015 - 2018 CRYPTACUS - Cryptanalysis of ubiquitous computing systems
ICT COST Action IC1403
Researcher
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
Concluded
2015 - 2018 ReThink - Smart Networks and novel Internet Architectures
H2020, ref. 645342
Researcher
2014 - 2017 EMC2 - Embedded Multi-Core Systems for Mixed Criticality Applications in Dynamic and Changeable Real-Time Environments
ARTEMIS/0003/2013
Researcher
Concluded
2012 - 2016 TRUDEVICE - Trustworthy Manufacturing and Utilization of Secure Device
ICT COST Action IC1204
Researcher
2014 - 2015 FARNuSyC - Framework for Automatic RNS-Based Computation
EXPL/EEI-ELC/1572/2013
Principal investigator
Concluded
2011/01/01 - 2013/12/31 HELIX: Arquitectura heterogénea com múltiplos núcleos para análise de sequências biológicas
PTDC/EEA-ELC/113999/2009
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia
Concluded
2009 - 2011 Sideworks - Reconfigurable Processor, Compiler and Applications
3487
Post-doc
Quadro de Referência Estratégica Nacional
Concluded
Outputs

Publications

Book
  1. Sklavos, N.; Chaves, R.; Di Natale, G.; Regazzoni, F.. Preface. 2017.
  2. Nicolas Sklavos; Ricardo Chaves; Giorgio Di Natale; Francesco Regazzoni. Hardware Security and Trust. Switzerland. 2016.
  3. Resende, J.C.; Chaves, R.. Dual CLEFIA/AES cipher core on FPGA. 2015.
    10.1007/978-3-319-16214-0_19
  4. Colaço, J.; Matoga, A.; Ilic, A.; Roma, N.; Tomás, P.; Chaves, R.. Transparent application acceleration by intelligent scheduling of shared library calls on heterogeneous systems. 2014.
    10.1007/978-3-642-55224-3_65
  5. Chaves, R.; Donchev, B.; Kuzmanov, G.; Sousa, L.; Vassiliadis, S.. BRAM-LUT tradeoff on a polymorphic des design. 2008.
    10.1007/978-3-540-77560-7_5
  6. Chaves, R.; Kuzmanov, G.; Sousa, L.; Vassiliadis, S.. Rescheduling for optimized SHA-1 calculation. 2006.
    10.1007/11796435_43
  7. Chaves, R.; Kuzmanov, G.; Sousa, L.; Vassiliadis, S.. Improving SHA-2 hardware implementations. 2006.
    10.1007/11894063_24
Book chapter
  1. "European Processor Initiative". In HPC, Big Data, and AI Convergence Towards Exascale. 2022.
  2. Chaves, Ricardo. "SCA-Resistance for AES: How Cheap Can We Go?". 2018.
    10.1007/978-3-319-89339-6_7
  3. Chaves, R.; Sousa, L.; Sklavos, N.; Fournaris, A.P.; Kalogeridou, G.; Kitsos, P.; Sheikh, F.. "Secure hashing: SHA-1, SHA-2, and SHA-3". 81-107. 2017.
  4. Matutino, P.M.; Chaves, R.; Sousa, L.. "RNS-based embedded processor design". 19-47. 2017.
  5. Resende, J.C.; Chaves, R.. "AES datapaths on FPGAs: A state of the art analysis". 1-25. 2017.
  6. Chaves, R.; Proença, P.. "Compact CLEFIA implementation on FPGAs". In Proceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011, 225-243. 2013.
    10.1109/FPL.2011.101
  7. Antão, S.; Chaves, R.; Sousa, L.. "Reconfigurable Architecture for Cryptography over Binary Finite Fields". In Embedded Systems: Hardware, Design, and Implementation, 319-362. 2012.
Conference paper
  1. Resende, Joao Carlos; J. R. Macas, Ricardo; Chaves, Ricardo. "Mask Scrambling Against SCA on Reconfigurable TBOX-Based AES". 2020.
    10.1109/fpl50879.2020.00048
  2. Resende, J.C.; MacAs, R.J.R.; Chaves, R.. "TBOX-Based Mask Scrambling Against SCA". 2020.
    10.1109/FCCM48280.2020.00039
  3. Chaves, Ricardo; Leitao, J.M.; Chaves, R.; Santos, M.B.. "Applying Model Checking in the Verification of a Clock Masking Unit". 2019.
    10.1109/dcis201949030.2019.8959910
  4. Chaves, Ricardo; Capeleiro, R.; Leitão, J.M.; Chaves, R.; Santos, M.B.. "Low-power frequency monitoring circuit for clock failure detection". 2018.
    10.1109/dcis.2018.8681489
  5. Parrinha, D.; Chaves, R.; Chaves, Ricardo. "Flexible and low-cost HSM based on non-volatile FPGAs". 2018.
    10.1109/RECONFIG.2017.8279795
  6. Chaves, Ricardo. "Area-optimized montgomery multiplication on IGLOO 2 FPGAs". 2017.
    10.23919/FPL.2017.8056762
  7. Chaves, Ricardo; Matutino, P.M.; Araujo, J.; Sousa, L.; Chaves, R.. "Pipelined FPGA coprocessor for elliptic curve cryptography based on residue number system". 2017.
    10.1109/samos.2017.8344638
  8. Chaves, Ricardo. "Decentralized communications: Trustworthy interoperability in peer-to-peer networks". 2017.
    10.1109/EuCNC.2017.7980649
  9. Chaves, Ricardo. "Improving FPGA based SHA-3 structures". 2017.
    10.1109/HST.2017.7951823
  10. Sundal, M.; Chaves, R.; Chaves, Ricardo. "Efficient FPGA Implementation of the SHA-3 Hash Function". 2017.
    10.1109/ISVLSI.2017.24
  11. Pereira, S.; Alves, A.; Santos, N.; Chaves, R.. "Storekeeper: A Security-Enhanced Cloud Storage Aggregation Service". 2016.
    10.1109/SRDS.2016.023
  12. Resende, J.C.; Chaves, R.. "Compact dual block AES core on FPGA for CCM Protocol". 2015.
    10.1109/FPL.2015.7293948
  13. Matutino, P.M.; Chaves, R.; Sousa, L.. "ROM-less RNS-to-binary converter moduli {22n-1, 22n + 1, 2n-3, 2n + 3}". 2015.
    10.1109/ISICIR.2014.7029521
  14. Bittencourt, J.C.; Resende, J.C.; Oliveira, W.L.D.; Chaves, R.. "CLEFIA implementation with full key expansion". 2015.
    10.1109/DSD.2015.55
  15. Chaves, Ricardo. "Challenges in designing trustworthy cryptographic co-processors". 2015.
    10.1109/ISCAS.2015.7169070
  16. Kashyap, H.; Chaves, R.. "Secure partial dynamic reconfiguration with unsecured external memory". 2014.
    10.1109/FPL.2014.6927477
  17. Amaral, J.; Regazzoni, F.; Tomas, P.; Chaves, R.. "Accelerating Differential Power Analysis on heterogeneous systems". 2014.
    10.1145/2668322.2668326
  18. Pettenghi, H.; Ambrose, J.A.; Chaves, R.; Sousa, L.. "Method for designing multi-channel RNS architectures to prevent power analysis SCA". 2014.
    10.1109/ISCAS.2014.6865614
  19. Leitao, J.; Germano, J.; Roma, N.; Chaves, R.; Tomas, P.. "Scalable and high throughput biosensing platform". 2013.
    10.1109/FPL.2013.6645529
  20. Matoga, A.; Chaves, R.; Tomas, P.; Roma, N.. "A flexible shared library profiler for early estimation of performance gains in heterogeneous systems". 2013.
    10.1109/HPCSim.2013.6641454
  21. Paiágua, S.; Pratas, F.; Tomás, P.; Roma, N.; Chaves, R.. "HotStream: Efficient data streaming of complex patterns to multiple accelerating kernels". 2013.
    10.1109/SBAC-PAD.2013.17
  22. Antão, S.; Chaves, R.; Sousa, L.. "Efficient FPGA elliptic curve cryptographic processor over GF(2m)". 2008.
    10.1109/FPT.2008.4762417
  23. Chaves, R.; Sousa, L.. "{2n + 1, 2n+k, 2n - 1}: A new RNS moduli set extension". 2004.
    10.1109/DSD.2004.1333279
Edited book
  1. Chaves, Ricardo. Hardware Security and Trust. Springer International Pu. 2017.
    10.1007/978-3-319-44318-8
Journal article
  1. Francisco Eugenio Potestad-Ordóñez; Erica Tena-Sánchez; Antonio José Acosta-Jiménez; Carlos Jesús Jiménez-Fernández; Ricardo Chaves. "Hardware Countermeasures Benchmarking against Fault Attacks". Applied Sciences (2022): https://doi.org/10.3390/app12052443.
    10.3390/app12052443
  2. Erica Tena-Sánchez; Francisco Eugenio Potestad-Ordóñez; Carlos J. Jiménez-Fernández; Antonio J. Acosta; Ricardo Chaves. "Gate-Level Hardware Countermeasure Comparison against Power Analysis Attacks". Applied Sciences 12 5 (2022): 2390-2390. https://doi.org/10.3390/app12052390.
    10.3390/app12052390
  3. "Hardware Countermeasures Benchmarking against Fault Attacks". (2022):
    https://doi.org/10.3390/app12052443
  4. "Gate-Level Hardware Countermeasure Comparison against Power Analysis Attacks". (2022):
    Published • https://doi.org/10.3390/app12052390
  5. Javed, I.T.; Copeland, R.; Crespi, N.; Emmelmann, M.; Corici, A.; Bouabdallah, A.; Zhang, T.; et al. "Cross-domain identity and discovery framework for web calling services". Annales des Telecommunications/Annals of Telecommunications 72 7-8 (2017): 459-468. http://www.scopus.com/inward/record.url?eid=2-s2.0-85021217603&partnerID=MN8TOARS.
    10.1007/s12243-017-0587-2
  6. Hector Pettenghi; Ricardo Chaves; Roberto de Matos; Leonel Sousa. "Method for designing two levels RNS reverse converters for large dynamic ranges". Integration 55 (2016): 22-29. https://doi.org/10.1016/j.vlsi.2016.02.004.
    10.1016/j.vlsi.2016.02.004
  7. Chaves, Ricardo. "Compact and on-the-fly secure dynamic reconfiguration for volatile fpgas". ACM Transactions on Reconfigurable Technology and Systems (TRETS) 9 2 (2016): 11-11.
    10.1145/2816822
  8. Matutino, P.M.; Chaves, R.; Sousa, L.. "Arithmetic-based binary-to-RNS converter modulo {2n±k} for -bit dynamic range". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 3 (2015): 603-607. http://www.scopus.com/inward/record.url?eid=2-s2.0-85027920645&partnerID=MN8TOARS.
    10.1109/TVLSI.2014.2314174
  9. Neves, N.; Mendes, H.; Chaves, R.J.; Tomás, P.; Roma, N.. "Morphable hundred-core heterogeneous architecture for energy-aware computation". IET Computers and Digital Techniques 9 1 (2015): 49-62. http://www.scopus.com/inward/record.url?eid=2-s2.0-84921038801&partnerID=MN8TOARS.
    10.1049/iet-cdt.2014.0078
  10. Matutino, P.M.; Chaves, R.; Sousa, L.. "An Efficient Scalable RNS Architecture for Large Dynamic Ranges". Journal of Signal Processing Systems 77 1-2 (2014): 191-205. http://www.scopus.com/inward/record.url?eid=2-s2.0-84920253342&partnerID=MN8TOARS.
    10.1007/s11265-014-0875-2
  11. Pettenghi, H.; Chaves, R.; Sousa, L.. "RNS reverse converters for moduli sets with dynamic ranges up to (8n+1)-bit". IEEE Transactions on Circuits and Systems I: Regular Papers 60 6 (2013): 1487-1500. http://www.scopus.com/inward/record.url?eid=2-s2.0-84878421822&partnerID=MN8TOARS.
    10.1109/TCSI.2012.2220460
  12. Sousa, L.; Antao, S.; Chaves, R.. "On the Design of RNS Reverse Converters for the Four-Moduli Set{2 s + 1, 2n-1, 2n, 2n+1 + 1}". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 10 (2013): 1945-1949. http://www.scopus.com/inward/record.url?eid=2-s2.0-84884576977&partnerID=MN8TOARS.
    10.1109/TVLSI.2012.2219564
  13. Matutino, P.M.; Chaves, R.; Sousa, L.. "A compact and scalable RNS architecture". Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors (2013): 125-132. http://www.scopus.com/inward/record.url?eid=2-s2.0-84883441961&partnerID=MN8TOARS.
    10.1109/ASAP.2013.6567565
  14. Pettenghi, H.; Chaves, R.; Sousa, L.. "Method to design general RNS reverse converters for extended moduli sets". IEEE Transactions on Circuits and Systems II: Express Briefs 60 12 (2013): 877-881. http://www.scopus.com/inward/record.url?eid=2-s2.0-84890858239&partnerID=MN8TOARS.
    10.1109/TCSII.2013.2286433
  15. Matutino, P.M.; Pettenghi, H.; Chaves, R.; Sousa, L.. "RNS arithmetic units for modulo {2n±k}". Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012 (2012): 795-802. http://www.scopus.com/inward/record.url?eid=2-s2.0-84872972750&partnerID=MN8TOARS.
    10.1109/DSD.2012.114
  16. Castro, C.F.; Sousa, L.C.; Chaves, R.; António, C.C.; Santos, R.; Castro, P.; Azevedo, E.. "Mesh generation and blood flow simulation in human carotid bifurcation". Civil-Comp Proceedings 100 (2012): http://www.scopus.com/inward/record.url?eid=2-s2.0-84893856677&partnerID=MN8TOARS.
  17. Matutino, P.M.; Chaves, R.; Sousa, L.. "Binary-to-RNS conversion units for moduli {2 n ± 3}". Proceedings - 2011 14th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2011 (2011): 460-467. http://www.scopus.com/inward/record.url?eid=2-s2.0-80054983594&partnerID=MN8TOARS.
    10.1109/DSD.2011.65
  18. Gbolagade, K.A.; Chaves, R.; Sousa, L.; Cotofana, S.D.. "An improved RNS reverse converter for the {22n+1-1,2 n,2n-1} moduli set". ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems (2010): 2103-2106. http://www.scopus.com/inward/record.url?eid=2-s2.0-77955999090&partnerID=MN8TOARS.
    10.1109/ISCAS.2010.5537062
  19. Matutino, P.M.; Chaves, R.; Sousa, L.. "Arithmetic units for RNS moduli {2n - 3} and {2n + 3} operations". Proceedings - 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2010 (2010): 243-246. http://www.scopus.com/inward/record.url?eid=2-s2.0-78649810172&partnerID=MN8TOARS.
    10.1109/DSD.2010.77
  20. Pettenghi, H.; Chaves, R.; Sousa, L.; Avedillo, M.J.. "An improved RNS generator 2n ± k based on threshold logic". Proceedings of the 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010 (2010): 119-124. http://www.scopus.com/inward/record.url?eid=2-s2.0-78650934297&partnerID=MN8TOARS.
    10.1109/VLSISOC.2010.5642611
  21. Gbolagade, K.A.; Chaves, R.; Sousa, L.; Cotofana, S.D.. "Residue-to-binary converters for the moduli set {22n+1-1,2 2n,2n-1}". ICAST 2009 - 2nd International Conference on Adaptive Science and Technology (2009): 26-33. http://www.scopus.com/inward/record.url?eid=2-s2.0-77950954216&partnerID=MN8TOARS.
    10.1109/ICASTECH.2009.5409752
  22. Antao, Samuel; Chaves, Ricardo; Sousa, Leonel; IEEE Computer Soc. "Compact and Flexible Microcoded Elliptic Curve Processor for Reconfigurable Devices". Proceedings of the 2009 17th Ieee Symposium on Field Programmable Custom Computing Machines (2009): 193-200.
    10.1109/FCCM.2009.18
  23. Pericàs, M.; Chaves, R.; Gaydadjiev, G.N.; Vassiliadis, S.; Valero, M.. "Vectorized AES core for high-throughput secure environments". Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 5336 LNCS (2008): 83-94. http://www.scopus.com/inward/record.url?eid=2-s2.0-58349088504&partnerID=MN8TOARS.
    10.1007/978-3-540-92859-1_10
  24. Chaves, R.; Kuzmanov, G.; Sousa, L.; Vassiliadis, S.. "Merged computation for Whirlpool hashing". Proceedings -Design, Automation and Test in Europe, DATE (2008): 272-275. http://www.scopus.com/inward/record.url?eid=2-s2.0-49749088708&partnerID=MN8TOARS.
    10.1109/DATE.2008.4484896
  25. Chaves, R.; Kuzmanov, G.; Sousa, L.. "On-the-fly attestation of reconfigurable hardware". Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL (2008): 71-76. http://www.scopus.com/inward/record.url?eid=2-s2.0-54949141187&partnerID=MN8TOARS.
    10.1109/FPL.2008.4629910
  26. Chaves, Ricardo; Kuzmanov, Georgi; Sousa, Leonel; Vassiliadis, Starnatis. "Cost-efficient SHA hardware accelerators". Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 16 8 (2008): 999-1008.
    10.1109/TVLSI.2008.2000450
  27. Chaves, R.C.; Freitas, P.P.; Ocker, B.; Maass, W.. "MgO based picotesla field sensors". Journal of Applied Physics 103 7 (2008): http://www.scopus.com/inward/record.url?eid=2-s2.0-42149122687&partnerID=MN8TOARS.
    10.1063/1.2839311
  28. Borme, J.; Freitas, A.S.; Cardoso, S.; Almeida, J.M.; Chaves, R.C.; Freitas, P.P.. "Magnetoresistive-based static tester for actuators". Journal of Applied Physics 103 7 (2008): http://www.scopus.com/inward/record.url?eid=2-s2.0-42149088351&partnerID=MN8TOARS.
    10.1063/1.2838342
  29. Trindade, I.G.; Fermento, R.; Sousa, J.B.; Chaves, R.C.; Cardoso, S.; Freitas, P.P.. "Linear field amplification for magnetoresistive sensors". Journal of Applied Physics 103 10 (2008): http://www.scopus.com/inward/record.url?eid=2-s2.0-44649085602&partnerID=MN8TOARS.
    10.1063/1.2936315
  30. Trindade, I.G.; Teixeira, J.; Fermento, R.; Sousa, J.B.; Cardoso, S.; Chaves, R.C.; Freitas, P.P.. "High sensitivity spin valve sensors with AF coupled flux guides". IEEE Transactions on Magnetics 44 11 PART 2 (2008): 2472-2474. http://www.scopus.com/inward/record.url?eid=2-s2.0-59849103006&partnerID=MN8TOARS.
    10.1109/TMAG.2008.2002602
  31. Chaves, R.; Sousa, L.. "Improving residue number system multiplication with more balanced moduli sets and enhanced modular arithmetic structures". IET Computers and Digital Techniques 1 5 (2007): 472-480. http://www.scopus.com/inward/record.url?eid=2-s2.0-34548707033&partnerID=MN8TOARS.
    10.1049/iet-cdt:20060059
  32. Chaves, R.C.; Freitas, P.P.; Ocker, B.; Maass, W.. "Low frequency picotesla field detection using hybrid MgO based tunnel sensors". Applied Physics Letters 91 10 (2007): http://www.scopus.com/inward/record.url?eid=2-s2.0-34548514421&partnerID=MN8TOARS.
    10.1063/1.2775802
  33. Chaves, R.; Kuzmanov, G.; Vassiliadis, S.; Sousa, L.. "Reconfigurable memory based AES Co-processor". 20th International Parallel and Distributed Processing Symposium, IPDPS 2006 2006 (2006): http://www.scopus.com/inward/record.url?eid=2-s2.0-33847161354&partnerID=MN8TOARS.
    10.1109/IPDPS.2006.1639441
  34. Sousa, L.A.; Chaves, R.. "Erratum: "A universal architecture for designing efficient modulo 2n + 1 multipliers" (IEEE Transactions on Circuits and Systems - I: Regular Papers)". IEEE Transactions on Circuits and Systems I: Regular Papers 52 9 (2005): http://www.scopus.com/inward/record.url?eid=2-s2.0-27144539328&partnerID=MN8TOARS.
    10.1109/TCSI.2005.856130
  35. Sousa, L.A.; Chaves, R.. "A universal architecture for designing efficient modulo 2n + 1 multipliers". IEEE Transactions on Circuits and Systems I: Regular Papers 52 6 (2005): 1166-1178. http://www.scopus.com/inward/record.url?eid=2-s2.0-22144485617&partnerID=MN8TOARS.
    10.1109/TCSI.2005.849143
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Activities

Supervision

Thesis Title
Role 		Degree Subject (Type)
Institution / Organization
2010 - Current Over 40 MSc concluded supervisons
Supervisor
Universidade de Lisboa Instituto Superior Técnico, Portugal
2009 - 2015 Residue Number Systems: Efficient Architectures and Circuits
Supervisor of Pedro Miguel Florindo Miguens Matutino
 Engenharia Electrotécnica e de Computadores (PhD)
Universidade de Lisboa Instituto Superior Técnico, Portugal

Event organisation

Event name
Type of event (Role) 		Institution / Organization
2009 - Current Organização da conferencia ISPDC'2009 - International Symposium on Parallel and Distributed Computing (2009/06/30 - 2009/07/04)
Conference (Co-organisor)
 Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
2018/04 - 2018/04 CRYPACUS 2018 training school (2018/04 - 2018/04)
Other (President of the Organising Committee)
 Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
2014 - 2014 TRUDEVICE 2014 training school (2014 - 2014)
Other (President of the Organising Committee)
 Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
Distinctions

Other distinction

2016 IEEE Senior Member
IEEE, United States