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João Bispo is an assistant professor at the Faculty of Engineering, University of Porto (FEUP), coordinator of the Special-Purpose Computing Systems, languages and tools (SPeCS) research group, integrated in the COMputational SYStems (COMPSYS) lab of the Informatics Engineering Department (DEI) in FEUP, and area coordinator in INESCTEC’s HumanISE centre. During 2012-2016, his main line of research was MATLAB to C compilation, and was the main developer of the tool MATISSE. He was University of Porto team leader of the European H2020 project ANTAREX, where he developed tools and techniques based on C/C++ source-to-source transformations and optimizations for high-performance and distributed computers, being the main developer of the Clava C/C++ source-to-source compiler. Clava continues to be used for research, and recently has been used as the basis for a Rust-inspired borrow-checker for the C language. He is doing research since the end of his bachelor's (2006), and during this time he has had the opportunity to work in several national and international projects, and to contribute with excellent science in several subjects. For instance, his work on hardware synthesis of regular expressions includes two seminal publications which sum close to 400 citations (according to Google Scholar) that have become a reference in the field; he has extensive experience on hardware synthesis from high-level descriptions, including the development of a Perl-Compatible Regular Expressions (PCRE) to HDL (with CE at Delft University of Technology), and a custom VLIW architecture description to HDL (with ITIV at Karlsruhe Institute of Technology (KIT)). The PhD focused on detecting and migrating runtime loops in MicroBlaze assembly traces to customized hardware.
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Identification

Personal identification

Full name
João Carlos Viegas Martins Bispo

Citation names

  • BISPO, JOÃO

Author identifiers

Ciência ID
121D-D25C-4FAE
ORCID iD
0000-0002-3017-9449

Knowledge fields

  • Engineering and Technology - Electrotechnical Engineering, Electronics and Informatics - Computer Hardware and Architecture
  • Engineering and Technology - Electrotechnical Engineering, Electronics and Informatics - Computer Hardware and Architecture
  • Exact Sciences - Computer and Information Sciences - Computer Sciences
  • Exact Sciences - Computer and Information Sciences - Computer Sciences

Languages

Language Speaking Reading Writing Listening Peer-review
English Advanced (C1) Advanced (C1) Advanced (C1) Advanced (C1)
Spanish; Castilian Advanced (C1) Advanced (C1) Intermediate (B1) Advanced (C1)
French Beginner (A1) Intermediate (B1) Beginner (A1) Beginner (A1)
Education
Degree Classification
2007/10 - 2012/07
Concluded
 Programa Doutoral em Engenharia Informática e de Computadores (Doutoramento)
Universidade de Lisboa Instituto Superior Técnico, Portugal
"Mapping Runtime-Detected Loops from Microprocessors to Reconfigurable Processing Units" (THESIS/DISSERTATION)
 Pass with Merit
2006
Concluded
 Engenharia de Sistemas e Informática (Licenciatura)
Universidade do Algarve Faculdade de Ciências e Tecnologia, Portugal
"Regular Expression Matching For Reconfigurable Packet Inspection" (THESIS/DISSERTATION)
 16
Affiliation

Science

Category
Host institution 		Employer
2016/01/01 - 2020/08/31 Postdoc (Research) Universidade do Porto Faculdade de Engenharia, Portugal
Instituto de Engenharia de Sistemas e Computadores Tecnologia e Ciência, Portugal
(...)

Teaching in Higher Education

Category
Host institution 		Employer
2020/09/02 - Current Assistant Professor (University Teacher) Universidade do Porto Faculdade de Engenharia, Portugal
Universidade do Porto Faculdade de Engenharia, Portugal
2019/09/01 - 2020/08/31 Invited Assistant Professor (University Teacher) Universidade do Porto Faculdade de Engenharia, Portugal
Universidade do Porto Faculdade de Engenharia, Portugal

Others

Category
Host institution 		Employer
2017/03/01 - 2020/09/01 Bolsa de Pós-Doutoramento FCT SFRH / BPD / 118211 / 2016 Universidade do Porto Faculdade de Engenharia, Portugal
Universidade do Porto Faculdade de Engenharia, Portugal
(...)
2015/09/01 - 2019/01/31 UPORTO Team Leader in the H2020 project ANTAREX - AutoTuning and Adaptivity appRoach for Energy efficient eXascale HPC systems Universidade do Porto Faculdade de Engenharia, Portugal
SPeCS Lab - Special-Purpose Computing Systems, languages and tools, Portugal
2016/10/19 - 2016/11/09 Organizing the 1st Programming and Optimizing for Performance (POP'16) Competition (http://specs.fe.up.pt/pop16/) Universidade do Porto Faculdade de Engenharia, Portugal
SPeCS Lab - Special-Purpose Computing Systems, languages and tools, Portugal
2013/07/01 - 2015/06/30 Postdoc researcher in the project LATiCES - Languages And Tools for Critical rEal-time Systems Universidade do Porto Faculdade de Engenharia, Portugal
SPeCS Lab - Special-Purpose Computing Systems, languages and tools, Portugal
2012/04/01 - 2013/07/31 Researcher in the FP7 project REFLECT - Rendering FPGAs to Multi-Core Embedded Computing Universidade do Porto Faculdade de Engenharia, Portugal
SPeCS Lab - Special-Purpose Computing Systems, languages and tools, Portugal
2006/10/01 - 2007/09/30 BID - Bolsa Intercalar de Doutoramento Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
2006/10/11 - 2006/11/25 Guest Investigator Karlsruher Institut für Technologie, Germany
2006/02/03 - 2006/06/30 Guest Investigator Technische Universiteit Delft Faculteit Elektrotechniek Wiskunde en Informatica, Netherlands
2005/09/15 - 2005/12/20 VHDL Programmer, Hardware Designer Universidade do Algarve, Portugal
2004/07/15 - 2004/09/15 Programmer Universidade do Algarve - Campus de Gambelas, Portugal
SipLab - Laboratório de Sinais da Universidade do Algarve, Portugal
2001/07/01 - 2001/08/15 Programmer, Electronics Technician Universidade do Algarve - Campus de Gambelas, Portugal
LIP - Laboratório de Instrumentação e Física Experimental de Partículas da Universidade do Algarve, Portugal
Projects

Grant

Designation Funders
2017/03/01 - 2020/09/01 Research on Recipes For Mapping Computations to Heterogeneous Computing Systems
SFRH/BPD/118211/2016
 Fundação para a Ciência e a Tecnologia
Concluded
2007/10/01 - 2011/09/30 COMPILAÇÃO JIT JUST-IN-TIME PARA ARQUITECTURAS COMPUTACIONAIS PERSONALIZÁVEIS DURANTE A EXECUÇÃO
SFRH/BD/36735/2007
 Fundação para a Ciência e a Tecnologia
Concluded

Contract

Designation Funders
2020/11/01 - Current PRACE 6th Implementation Phase Project
823767
Researcher
European Commission
Ongoing
2020/09/01 - Current PRACE-6IP - PRACE 6th Implementation Phase Project (823767)
PRACE-6IP
Researcher
2023/03/10 - 2026/03/09 Compilação e Adaptação de Hardware para a Unificação da Computação Especializada e de Uso Geral
2022.06780.PTDC
10.54499/2022.06780.PTDC
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal

Instituto de Telecomunicações Lisboa, Portugal

Instituto de Engenharia de Sistemas e Computadores Tecnologia e Ciência, Portugal
Fundação para a Ciência e a Tecnologia
Ongoing
2023/01/01 - 2025/12/31 Artificial Intelligence using Quantum measured Information for realtime distributed systems at the edge
101096658
Researcher
2020/07/01 - 2023/06/30 THEIA - Automated Perception Driving
POCI-01-0247-FEDER-047264
Researcher
2016/06/01 - 2019/12/31 Middleware e Técnicas de Inferência de Contextos a partir de fluxos de Dados para Desenvolvimento de Serviços Conscientes do Contexto em Dispositivos Móveis
PTDC/EEI-SCR/6945/2014
Instituto de Engenharia de Sistemas e Computadores, Portugal

Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
Fundação para a Ciência e a Tecnologia
Concluded
2019/06/01 - 2019/11/30 Middleware and Context Inference Techniques from Data-Streams for the Development of Context-Aware Services using Mobile Devices
POCI-01-0145-FEDER-016883
Post-doc Fellow
2015/09/01 - 2018/10/31 AutoTuning and Adaptivity appRoach for Energy efficient eXascale HPC systems
info:eu-repo/grantAgreement/EC/H2020/671623/EU
 Fundação para a Ciência e a Tecnologia
2013/07/01 - 2015/06/30 BESTCASE-RL8-REALTIME: Languages and tools for critical real time systems
NORTE-01-0124-FEDER-000062
Post-doc Fellow
Concluded
2010/01/01 - 2013/06/30 Rendering FPGAs to Multi-Core Embedded Computing
info:eu-repo/grantAgreement/EC/FP7/248976/EU
 Fundação para a Ciência e a Tecnologia
2007/10/01 - 2011/03/31 COBAYA: DIMINUIÇÃO DO INTERVALO ENTRE COMPILAÇÃO DE ALGORITMOS E ARQUITECTURAS MATRICIAIS RECONFIGURÁVEIS DE GRANULOSIDADE GROSSA
PTDC/EEA-ELC/70272/2006
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal

Universidade do Porto Faculdade de Engenharia, Portugal
Fundação para a Ciência e a Tecnologia
Concluded
2007/10/01 - 2008/09/30 COBAYA: CLOSING THE COMPILATION GAP BETWEEN ALGORITHMS AND COARSE-GRAINED RECONFIGURABLE ARRAY ARCHITECTURES
info:eu-repo/grantAgreement/FCT/3599-PPCDT/70272/PT
 Fundação para a Ciência e a Tecnologia
Concluded
2006/10/01 - 2007/09/30 Architecture and Compilation Exploration for a Dynamically Reconfigurable System-on-Chip (ACER)
Acções Integradas - 2007, CRUP/DAAD
Scientific Initiation Fellow
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia
Concluded
Outputs

Publications

Book
  1. Faculdade de Engenharia. The ANTAREX tool flow for monitoring and autotuning energy efficient HPC systems. Portugal. 2017.
  2. Faculdade de Engenharia; Golasowski,M; João Bispo; Martinovic,J; Slaninová,K; João Paiva Cardoso; Golasowski, M.; et al. Expressing and Applying C plus plus Code Transformations for the HDF5 API Through a DSL. Portugal. 2017.
    http://dx.doi.org/10.1007/978-3-319-59105-6_26
  3. Cardoso, J.M.P.; Bispo, J.; Sanches, A.K.. The role of programming models on reconfigurable computing fabrics. 2009.
    10.4018/978-1-60566-750-8.ch012
  4. Faculdade de Engenharia; Morra, C.; Cardoso, J.M.P.; Bispo, J.; Becker, J.. Retargeting, evaluating, and generating reconfigurable array-based architectures. Portugal. 2008.
    10.1109/SASP.2008.4570783
Conference paper
  1. Tiago Silva; BISPO, JOÃO; Carvalho, Tiago. Corresponding author: BISPO, JOÃO. "Foundations for a Rust-Like Borrow Checker for C". Paper presented in Languages, Compilers, Tools and Theory of Embedded Systems (LCTES), Copenhagen, 2024.
    Accepted
  2. Manuel Cerqueira da Silva; Sousa, Luís; Paulino, Nuno; BISPO, JOÃO. Corresponding author: Manuel Cerqueira da Silva. "A DSL and MLIR Dialect for Streaming and Vectorisation". Paper presented in ARC 2024 : Applied Reconfigurable Computing, Aveiro, 2024.
    Published
  3. João N. Matos; João Bispo; Luís Miguel Sousa. "A C Subset for Ergonomic Source-to-Source Analyses and Transformations". 2024.
    10.1145/3642921.3642922
  4. Luís Miguel Henriques; BISPO, JOÃO; Paulino, Nuno. Corresponding author: BISPO, JOÃO. "Using Source-to-Source to Target RISC-V Custom Extensions: UVE Case-Study". Paper presented in 16th Workshop on Rapid Simulation and Performance Evaluation for Design Optimization: Methods and Tools (RAPIDO), Munique, 2024.
    Published
  5. Bispo, J; Paulino, N; Sousa, LM. "Challenges and Opportunities in C/C++ Source-To-Source Compilation (Invited Paper)". 2023.
    10.4230/oasics.parma-ditam.2023.2
  6. Sousa, LM; Paulino, N; Ferreira, JC; Bispo, J. "A Flexible HLS Hoeffding Tree Implementation for Runtime Learning on FPGA". 2022.
    10.1109/melecon53508.2022.9843092
  7. Gregório, N; Fernandes, JP; Bispo, J; Medeiros, S. "E-APK: Energy Pattern Detection in Decompiled Android Applications". 2022.
    10.1145/3561320.3561328
  8. Gil Teixeira; João Bispo; Filipe F. Correia. "Multi-language static code analysis on the LARA framework". 2021.
    10.1145/3460946.3464317
  9. Silva, PF; Bispo, J; Paulino, N. "FPGAs as General-Purpose Accelerators for Non-Experts via HLS: The Graph Analysis Example". 2021.
    10.1109/icfpt52863.2021.9609832
  10. Santos, T; Paulino, N; Bispo, J; Cardoso, JMP; Ferreira, JC. "On the Performance Effect of Loop Trace Window Size on Scheduling for Configurable Coarse Grain Loop Accelerators". 2021.
    10.1109/icfpt52863.2021.9609868
  11. Paulino, N; Ferreira, JC; Bispo, J; Cardoso, JMP. "Executing ARMv8 Loop Traces on Reconfigurable Accelerator via Binary Translation Framework". 2020.
    10.1109/fpl50879.2020.00072
  12. Moreira, E; Correia, FF; Bispo, J. "Overviewing the liveness of refactoring for energy efficiency". 2020.
    10.1145/3397537.3397538
  13. Silvano, Cristina; Agosta, Giovanni; Bartolini, Andrea; Beccari, Andrea R.; Benini, Luca; Besnard, Loic; Bispo, Joao; et al. "Supporting the Scale-Up of High Performance Application to Pre-Exascale Systems: The ANTAREX Approach". 2019.
    10.1109/empdp.2019.8671584
  14. Silvano, C; Agosta, G; Bartolini, A; Beccari, AR; Benini, L; Besnard, L; Bispo, J; et al. "Supporting the Scale-up of High Performance Application to Pre-Exascale Systems: The ANTAREX Approach". 2019.
    10.1109/pdp.2019.00024
  15. Arabnejad, H; Bispo, J; Barbosa, JG; Cardoso, JMP. "An OpenMP based Parallelization Compiler for C Applications". 2018.
    10.1109/bdcloud.2018.00135
  16. Silvano, C; Agosta, G; Bartolini, A; Beccari, AR; Benini, L; Besnard, L; Bispo, J; et al. "ANTAREX: A DSL-Based Approach to Adaptively Optimizing and Enforcing Extra-Functional Properties in High Performance Computing". 2018.
    10.1109/DSD.2018.00105
  17. Arabnejad, H; Bispo, J; Barbosa, JG; Cardoso, JMP; Faculdade de Engenharia. "AutoPar-Clava: An Automatic Parallelization source-to-source tool for C code applications". 2018.
    10.1145/3183767.3183770
  18. Nobre, R; Reis, L; Bispo, J; Carvalho, T; Cardoso, JMP; Cherubin, S; Agosta, G; Faculdade de Engenharia. "Aspect-Driven Mixed-Precision Tuning Targeting GPUs". 2018.
    10.1145/3183767.3183776
  19. Silvano, C; Palermo, G; Agosta, G; Ashouri, AH; Gadioli, D; Cherubin, S; Vitali, E; et al. "Autotuning and Adaptivity in Energy Efficient HPC Systems: The ANTAREX Toolbox". 2018.
    10.1145/3203217.3205338
  20. Luís Cubal Reis; João Bispo; João Paiva Cardoso. "Compiler Techniques for Efficient MATLAB to OpenCL Code Generation". 2017.
    http://dx.doi.org/10.1145/3078155.3078186
  21. Silvano, C; Agosta, G; Barbosa, JG; Bartolini, A; Beccari, AR; Benini, L; Bispo, J; et al. "The ANTAREX tool flow for monitoring and autotuning energy efficient HPC systems". 2017.
    10.1109/samos.2017.8344645
  22. Pinto, P.; Carvalho, T.; Bispo, J.; Cardoso, J.M.P.; Faculdade de Engenharia; Pinto,P; Carvalho,T; João Bispo; João Paiva Cardoso. "LARA as a language-independent aspect-oriented programming approach". 2017.
    10.1145/3019612.3019749
  23. Reis, L.; Bispo, J.; Cardoso, J.M.P.. "Compiler techniques for efficient MATLAB to OpenCL code generation". 2017.
    10.1145/3078155.3078186
  24. Luís Cubal Reis; João Bispo; João Paiva Cardoso; Reis, L; Bispo, J; Cardoso, JMP. "SSA-based MATLAB-to-C compilation and optimization". 2016.
    http://dx.doi.org/10.1145/2935323.2935330
  25. Silvano,C; Agosta,G; Cherubin,S; Gadioli,D; Palermo,G; Bartolini,A; Benini,L; et al. "The ANTAREX approach to autotuning and adaptivity for energy efficient HPC systems". 2016.
    http://dx.doi.org/10.1145/2903150.2903470
  26. Silvano,C; Agosta,G; Bartolini,A; Beccari,AR; Benini,L; João Bispo; Cmar,R; et al. "AutoTuning and Adaptivity appRoach for Energy efficient eXascale HPC systems: the ANTAREX Approach". 2016.
  27. Silvano, C; Agosta, G; Cherubin, S; Gadioli, D; Palermo, G; Bartolini, A; Benini, L; et al. "The ANTAREX approach to autotuning and adaptivity for energy efficient HPC systems". 2016.
    10.1145/2903150.2903470
  28. João Bispo; Luís Cubal Reis; João Paiva Cardoso. "Techniques for efficient MATLAB-to-C compilation". 2015.
    http://dx.doi.org/10.1145/2774959.2774961
  29. João Bispo; Luís Cubal Reis; João Paiva Cardoso. "C and OpenCL Generation from MATLAB". 2015.
    http://dx.doi.org/10.1145/2695664.2695911
  30. Paulino, N; Ferreira, JC; Bispo, J; Cardoso, JMP; Nuno Miguel Paulino; João Canas Ferreira; João Bispo; João Paiva Cardoso. "Transparent acceleration of program execution using reconfigurable hardware". 2015.
    10.7873/date.2015.1122
  31. Bispo, J; Reis, L; Cardoso, JMP. "Techniques for efficient MATLAB-to-C compilation". 2015.
    10.1145/2774959.2774961
  32. Bispo, J; Reis, L; Cardoso, JMP. "C and OpenCL Generation from MATLAB". 2015.
    10.1145/2695664.2695911
  33. João Bispo; Luís Cubal Reis; João Paiva Cardoso. "Multi-target c code generation from MATLAB". 2014.
    http://dx.doi.org/10.1145/2627373.2627389
  34. Bispo, J.; Reis, L.; Cardoso, J.M.P.. "Multi-target c code generation from MATLAB". 2014.
    10.1145/2627373.2627389
  35. João Bispo; Pinto,P; Ricardo Ferreira Nobre; Carvalho,T; João Paiva Cardoso; Pedro Diniz. "The MATISSE MATLAB Compiler". 2013.
    http://dx.doi.org/10.1109/indin.2013.6622952
  36. Bispo, J.; Pinto, P.; Nobre, R.; Carvalho, T.; Cardoso, J.M.P.; Diniz, P.C.. "The MATISSE MATLAB compiler: A MATrix(MATLAB)-aware compiler InfraStructure for embedded computing SystEms". 2013.
    10.1109/INDIN.2013.6622952
  37. Bispo, J.; Cardoso, J.M.P.; Monteiro, J.. "Hardware pipelining of runtime-detected loops". 2012.
    10.1109/SBCCI.2012.6344443
  38. João Bispo; João Canas Ferreira; Nuno Paulino; João M.P. Cardoso. "From Instruction Traces to Specialized Reconfigurable Arrays". 2011.
  39. Bispo, J.; Cardoso, J.M.P.. "Techniques for dynamically mapping computations to coprocessors". 2011.
    10.1109/ReConFig.2011.86
  40. Bispo, J.; Paulino, N.; Cardoso, J.M.P.; Ferreira, J.C.. "From instruction traces to specialized reconfigurable arrays". 2011.
    10.1109/reconfig.2011.43
  41. Bispo, J.; Cardoso, J.M.P.. "On identifying and optimizing instruction sequences for dynamic compilation". 2010.
    10.1109/fpt.2010.5681454
  42. Bispo, J.; Cardoso, J.M.P.. "On identifying segments of traces for dynamic compilation". 2010.
    10.1109/fpl.2010.61
  43. Bispo, J.; Paiva, A.. "A model for emotional contagion based on the emotional contagion scale". 2009.
    10.1109/acii.2009.5349396
  44. Morra, C.; Bispo, J.; Cardoso, J.M.P.; Becke, J.; Faculdade de Engenharia. "Combining rewriting-logic, architecture generation, and simulation to exploit coarse-grained reconfigurable architectures". 2008.
    10.1109/fccm.2008.37
  45. Bispo, J.; Sourdis, I.; Cardoso, J.M.P.; Vassiliadis, S.. "Synthesis of regular expressions targeting FPGAs: Current status and open issues". 2007.
    10.1007/978-3-540-71431-6_17
  46. Bispo, J.; Sourdis, I.; Cardoso, J.M.P.; Vassiliadis, S.. "Regular expression matching for reconfigurable packet inspection". 2006.
    10.1109/fpt.2006.270302
Edited book
  1. Bispo, J; Charles, HP; Cherubin, S; Massari, G. 14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2023, January 17, 2023, Toulouse, France. 2023.
Journal article
  1. Nelson Gregório; João Bispo; João Paulo Fernandes; Sérgio Queiroz de Medeiros. "E-APK: Energy pattern detection in decompiled android applications". Journal of Computer Languages (2023): https://doi.org/10.1016/j.cola.2023.101220.
    10.1016/j.cola.2023.101220
  2. Carvalho, T; Bispo, J; Pinto, P; Cardoso, JMP. "A DSL-based runtime adaptivity framework for Java". SOFTWAREX (2023):
    10.1016/j.softx.2023.101496
  3. Ayesha Gauhar; Adnan Rashid; Osman Hasan; João Bispo; João M.P. Cardoso. "Formal verification of Matrix based MATLAB models using interactive theorem proving". PeerJ Computer Science (2021): https://doi.org/10.7717/peerj-cs.440.
    10.7717/peerj-cs.440
  4. Paulino, N; Bispo, J; Ferreira, JC; Cardoso, JMP. "A Binary Translation Framework for Automated Hardware Generation". IEEE MICRO (2021):
    10.1109/mm.2021.3088670
  5. Luís Reis; João Bispo; João M. P. Cardoso. "Compilation of MATLAB computations to CPU/GPU via C/OpenCL generation". Concurrency and Computation: Practice and Experience (2020): https://doi.org/10.1002/cpe.5854.
    10.1002/cpe.5854
  6. Carlos Alberto Oliveira de Souza Junior; João Bispo; João M. P. Cardoso; Pedro C. Diniz; Eduardo Marques. "Exploration of FPGA-Based Hardware Designs for QR Decomposition for Solving Stiff ODE Numerical Methods Using the HARP Hybrid Architecture". Electronics 9 5 (2020): 843-843. https://doi.org/10.3390/electronics9050843.
    10.3390/electronics9050843
  7. Bispo, J; Cardoso, JMP. "Clava: C/C plus plus source-to-source compilation using LARA". SOFTWAREX (2020):
    10.1016/j.softx.2020.100565
  8. Pinto, Pedro; Bispo, Joao; Cardoso, Joao; Barbosa, Jorge Gomes; Gadioli, Davide; Palermo, Gianluca; Martinovic, Jan; et al. "Pegasus: Performance Engineering for Software Applications Targeting HPC Systems". IEEE Transactions on Software Engineering (2020): 1-1. http://dx.doi.org/10.1109/tse.2020.3001257.
    In press • 10.1109/tse.2020.3001257
  9. Arabnejad, Hamid; Bispo, João; Cardoso, João M. P.; Barbosa, Jorge G.. "Source-to-source compilation targeting OpenMP-based automatic parallelization of C applications". The Journal of Supercomputing (2019): http://dx.doi.org/10.1007/s11227-019-03109-9.
    10.1007/s11227-019-03109-9
  10. Loïc Besnard; Pedro Pinto; Imane Lasri; João Bispo; Erven Rohou; João M.P. Cardoso. "A framework for automatic and parameterizable memoization". SoftwareX 10 (2019): 100322-100322. https://doi.org/10.1016/j.softx.2019.100322.
    10.1016/j.softx.2019.100322
  11. Nobre, R; Bispo, J; Carvalho, T; Cardoso, JMP. "Nonio — modular automatic compiler phase selection and ordering specialization framework for modern compilers". SoftwareX (2019):
    10.1016/j.softx.2019.100238
  12. Silvano, C; Agosta, G; Bartolini, A; Beccari, AR; Benini, L; Besnard, L; Bispo, J; et al. "The ANTAREX domain specific language for high performance computing". MICROPROCESSORS AND MICROSYSTEMS (2019):
    10.1016/j.micpro.2019.05.005
  13. Vitali, Emanuele; SILVANO, CRISTINA; Gadioli, Davide; Palermo, Gianluca; Golasowski, Martin; Bispo, Joao; Pinto, Pedro; et al. "An Efficient Monte Carlo-based Probabilistic Time-Dependent Routing Calculation Targeting a Server-Side Car Navigation System". IEEE Transactions on Emerging Topics in Computing (2019): 1-1. http://dx.doi.org/10.1109/tetc.2019.2919801.
    10.1109/tetc.2019.2919801
  14. Pinto, P; Carvalho, T; Bispo, J; Ramalho, MA; Cardoso, JMP. "Aspect composition for multiple target languages using LARA". COMPUTER LANGUAGES SYSTEMS & STRUCTURES (2018):
    10.1016/j.cl.2017.12.003
  15. João Bispo; João M. P. Cardoso. "A MATLAB subset to C compiler targeting embedded systems". Software: Practice and Experience (2017): https://doi.org/10.1002%2Fspe.2408.
    10.1002/spe.2408
  16. Bispo, J.; Paulino, N.; Cardoso, J.M.P.; Ferreira, J.C.. "Transparent runtime migration of loop-based traces of processor instructions to reconfigurable processing units". International Journal of Reconfigurable Computing 2013 (2013): http://www.scopus.com/inward/record.url?eid=2-s2.0-84874864892&partnerID=MN8TOARS.
    10.1155/2013/340316
  17. Bispo, J.; Cardoso, J.M.P.; Monteiro, J.. "Hardware pipelining of repetitive patterns in processor instruction traces". Journal of Integrated Circuits and Systems 8 1 (2013): 22-31. http://www.scopus.com/inward/record.url?eid=2-s2.0-84885355741&partnerID=MN8TOARS.
  18. Bispo, J.; Paulino, N.; Cardoso; Ferreira. "Transparent trace-based binary acceleration for reconfigurable HW/SW systems". IEEE Transactions on Industrial Informatics 9 3 (2013): 1625-1634. http://www.scopus.com/inward/record.url?eid=2-s2.0-84882945924&partnerID=MN8TOARS.
    10.1109/tii.2012.2235844
  19. Bispo, J.; Cardoso, J.M.P.. "Synthesis of regular expressions for FPGAs". International Journal of Electronics 95 7 (2008): 685-704. http://www.scopus.com/inward/record.url?eid=2-s2.0-49149092746&partnerID=MN8TOARS.
    10.1080/00207210801924107
  20. Sourdis, I.; Bispo, J.; Cardoso, J.M.P.; Vassiliadis, S.. "Regular expression matching in reconfigurable hardware". Journal of Signal Processing Systems 51 1 (2008): 99-121. http://www.scopus.com/inward/record.url?eid=2-s2.0-43449132689&partnerID=MN8TOARS.
    10.1007/s11265-007-0131-0

Other

Other output
  1. Building Beyond HLS: Graph Analysis and Others. 2021. Silva, PF; Bispo, J; Cardanha Paulino, NM.
  2. Aspect composition for multiple target languages using LARA. Usually, Aspect-Oriented Programming (AOP) languages are an extension of a specific target programming language (e.g., Aspect J for JAVA and Aspect C++ for C++). Although providing AOP support with target language extensions may ease the adoption of an approach, it may impose constraints related with constructs and semantics. Furthermore, by tightly coupling the AOP language to the target language. 2018. Faculdade de Engenharia. http://hdl.handle.net/10216/117169.
  3. A MATLAB subset to C compiler targeting embedded systems. This paper describes MATISSE, a compiler able to translate a MATLAB subset to C targeting embedded systems. MATISSE uses LARA, an aspect-oriented programming language, to specify additional information and transformations to the input MATLAB code, for example, insertion of code for initialization of variables, and specification of types and shapes of variables. The compiler is being developed bear. 2017. João Bispo; João Paiva Cardoso. http://repositorio.inesctec.pt/handle/123456789/6383.
    http://dx.doi.org/10.1002/spe.2408
  4. Hardware pipelining of repetitive patterns in processor instruction traces. Dynamic partitioning is a promising technique where computations are transparently moved from a General Purpose Processor (GPP) to a coprocessor during application execution. To be effective, the mapping of computations to the coprocessor needs to consider aggressive optimizations. One of the mapping optimizations is loop pipelining, a technique extensively studied and known to allow substantial p. 2013. João Bispo; João Paiva Cardoso; Monteiro,J. http://repositorio.inesctec.pt/handle/123456789/6393.
  5. Transparent runtime migration of loop-based traces of processor instructions to reconfigurable processing units. The ability to map instructions running in a microprocessor to a reconfigurable processing unit (RPU), acting as a coprocessor, enables the runtime acceleration of applications and ensures code and possibly performance portability. In this work, we focus on the mapping of loop-based instruction traces (called Megablocks) to RPUs. The proposed approach considers offline partitioning and mapping sta. 2013. João Bispo; Nuno Miguel Paulino; João Paiva Cardoso; João Canas Ferreira. http://repositorio.inesctec.pt/handle/123456789/5568.
    http://dx.doi.org/10.1155/2013/340316
  6. Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems. This paper presents a novel approach to accelerate program execution by mapping repetitive traces of executed instructions, called Megablocks, to a runtime reconfigurable array of functional units. An offline tool suite extracts Megablocks from microprocessor instruction traces and generates a Reconfigurable Processing Unit (RPU) tailored for the execution of those Megablocks. The system is able t. 2013. João Bispo; Nuno Miguel Paulino; João Paiva Cardoso; João Canas Ferreira. http://repositorio.inesctec.pt/handle/123456789/5564.
    http://dx.doi.org/10.1109/tii.2012.2235844
Activities

Supervision

Thesis Title
Role 		Degree Subject (Type)
Institution / Organization
2022/09/01 - Current Improving compilation workflows of heterogenous systems using source-to-source techniques
Supervisor of Luís Miguel Mendes Pimentel Alves de Sousa
 Doctoral Program in Electrical and Computer Engineering (PhD)
Universidade do Porto Faculdade de Engenharia, Portugal
2021/09/01 - Current A Holistic Approach for Partitioning and Optimizing Software Applications on FPGAs
Co-supervisor of Tiago Lascasas dos Santos
 Doctoral Program in Informatics Engineering (PhD)
Universidade do Porto Faculdade de Engenharia, Portugal