???global.info.a_carregar???
Jorge Guilherme. Concluiu o(a) Doutoramento em Engenharia Electrotécnica e de Computadores em 2003 pelo(a) Universidade de Lisboa Instituto Superior Técnico. É Professor Adjunto no(a) Instituto Politécnico de Tomar Escola Superior de Tecnologia de Tomar. Publicou 10 artigos em revistas especializadas e 62 artigos em Conferencias. Possui 4 capítulo(s) de livros e 4 livro(s). Possui 1 patente(s) registada(s). Atua na(s) área(s) de Ciências da Engenharia e Tecnologias com ênfase em Engenharia Eletrotécnica, Eletrónica e Informática com ênfase em Engenharia Eletrotécnica e Eletrónica. Nas suas atividades profissionais interagiu com 61 colaborador(es) em coautorias de trabalhos científicos. No seu currículo Ciência Vitae os termos mais frequentes na contextualização da produção científica, tecnológica e artístico-cultural são: Microelectronics; Data converters; Analog electronics; Power electronics; .
Read full resume ↓
Identification

Personal identification

Full name
Jorge Manuel Correia Guilherme

Author identifiers

Ciência ID
1D17-BACA-0534
ORCID iD
0000-0001-9304-4974

Email addresses

  • jorge.guilherme@ipt.pt (Professional)

Addresses

  • Instituto Politecnico Tomar, Quinta do contador, estrada da serra, 2300-313, Tomar, Tomar, Portugal (Professional)
  • Instituto Politécnico de Tomar. Escola Superior de Tecnologia de Tomar, 2300-313, Tomar, Tomar, Portugal (Professional)

Websites

Knowledge fields

  • Engineering and Technology - Electrotechnical Engineering, Electronics and Informatics - Electrical and Electronic Engineering
Education
Degree Classification
2003
Concluded
 Engenharia Electrotécnica e de Computadores (Doutoramento)
Major in Microelectronica
Universidade de Lisboa Instituto Superior Técnico, Portugal
"Architectures for High Dynamic Range Cmos Pipeline Analogue-to-digital Signal Conversion" (THESIS/DISSERTATION)
1992/09/01 - 1994/10/01
Concluded
 Mestrado Eng. Electrotecnica (Mestrado)
Major in Circuitos Integrados CMOS para Processamento e Conversão de Sinal em Sistemas de Radiocomunicações
Universidade de Lisboa Instituto Superior Técnico, Portugal
 Muito Bom
1984/09/01 - 1989/09/01
Concluded
 Engenharia Electrotecnica (Licenciatura)
Major in Telecomunicações
Universidade de Lisboa Instituto Superior Técnico, Portugal
 13
Affiliation

Science

Category
Host institution 		Employer
2004/09/01 - Current Researcher (Research) Instituto de Telecomunicações, Portugal

Teaching in Higher Education

Category
Host institution 		Employer
1996/05/01 - Current Adjunct Teacher (Polytechnic Teacher) Instituto Politécnico de Tomar Escola Superior de Tecnologia de Tomar, Portugal

Other Careers

Category
Host institution 		Employer
1980/01/01 - 1989/12/31 Coordenador Técnico (Assistente Técnico) ARAKIT, Portugal
Projects

Contract

Designation Funders
2020/01/01 - 2022/12/31 PROgrammable MIxed Signal Electronics - PROMISE
PROMISE
Researcher
Instituto de Telecomunicações, Portugal
 Thales Alenia Space
Ongoing
2013/10/01 - 2021/11/01 AIDA-C
AIDA-C
Researcher
Instituto de Telecomunicações, Portugal
Ongoing
2017/11/01 - 2020/10/31 INFANTE
INFANTE
Researcher
Instituto Politécnico de Tomar Escola Superior de Tecnologia de Tomar, Portugal
Concluded
2016/12/01 - 2019/06/30 UFLEXBAT
UFLEXBAT
Researcher
Instituto de Telecomunicações, Portugal
Concluded
2013/04/01 - 2016/12/01 DISRUPTIVE
DISRUPTIVE
Researcher
Instituto de Telecomunicações, Portugal

Associação para a Inovação e Desenvolvimento da FCT, Portugal

Universidade Nova de Lisboa UNINOVA Instituto de Desenvolvimento de Novas Tecnologias, Portugal
Concluded
2014/03/01 - 2016/02/01 OPERA
OPERA
Researcher
Concluded
2011/04/01 - 2014/04/01 Scales
info:eu-repo/grantAgreement/NSF/Directorate for Geosciences/9505742/US
Principal investigator
Thales Alenia Space, France
 Thales Alenia Space
Concluded
2011/10/01 - 2013/12/01 AIDA
AIDA
Researcher
Instituto de Telecomunicações, Portugal
Concluded
2011/07/01 - 2013/12/01 AISMAD
AISMAD
Principal investigator
Instituto de Telecomunicações, Portugal
Concluded
2008/11/01 - 2010/11/01 HEAD
HEAD
Principal investigator
Instituto de Telecomunicações, Portugal
Concluded
2008/10/01 - 2010/10/01 Space-DCDC
Space-DCDC
Principal investigator
Instituto de Telecomunicações, Portugal
Concluded
2005/08/01 - 2007/07/31 EVOLUTION
EVOLUTION
Researcher
Associação para a Inovação e Desenvolvimento da FCT, Portugal

Instituto de Telecomunicações, Portugal
Concluded
Outputs

Publications

Book
  1. Santos, M.; Horta, N.; Guilherme, J.. Preface. 2019.
    10.1016/B978-1-4160-6160-1.00165-4
  2. Guilherme, Jorge. Architectures for High Dynamic Range CMOS Pipeline ADC conversion. Germany. 2018.
  3. Silva, C.; Ayzac, P.; Horta, N.; Guilherme, J.. Nonlinearities behavioral modeling and analysis of pipelined ADC building blocks. 2015.
    10.1007/978-3-319-19872-9_8
  4. Canelas, A.; Martins, R.; Póvoa, R.; Lourenço, N.; Guilherme, J.; Horta, N.. Enhancing an automatic analog IC design flow by using a technology- independent module generator. 2014.
    10.4018/978-1-4666-6627-6.ch005
  5. Barros, M.F.M.; Guilherme, J.M.C.; Horta, N.C.G.. Studies in Computational Intelligence: Preface. 2010.
Book chapter
  1. Santos, M.; Guilherme, J.; Horta, N.. "Evaluation of the prototype". 95-109. 2019.
    10.1007/978-3-030-15978-8_6
  2. Santos, M.; Guilherme, J.; Horta, N.. "Future work and conclusions". 111-117. 2019.
    10.1007/978-3-030-15978-8_7
  3. Santos, M.; Guilherme, J.; Horta, N.. "Circuit and layout level validation". 75-94. 2019.
    10.1007/978-3-030-15978-8_5
  4. Santos, M.; Guilherme, J.; Horta, N.. "Nonlinear A/D converters". 11-36. 2019.
    10.1007/978-3-030-15978-8_2
  5. Santos, M.; Guilherme, J.; Horta, N.. "Logarithmic VTC design". 59-73. 2019.
    10.1007/978-3-030-15978-8_4
  6. Santos, M.; Guilherme, J.; Horta, N.. "Introduction". 1-10. 2019.
    10.1007/978-3-030-15978-8_1
  7. Santos, M.; Guilherme, J.; Horta, N.. "Logarithmic ADC". 37-58. 2019.
    10.1007/978-3-030-15978-8_3
  8. Guilherme, Jorge. "Automatic Layout Optimizations for Integrated MOSFET Power Stages". In Automatic Layout Optimizations for Integrated MOSFET Power Stages. 2015.
Conference paper
  1. Zangpo, J.; Dorji, G.; Guilherme, J.; Horta, N.. "A 302 uW CMOS temperature sensor to compensate frequency drift for an oscillator". 2019.
    10.1109/IEMECONX.2019.8877049
  2. Zangpo, J.; Povoa, R.; Guilherme, J.; Horta, N.. "An Integrated LC Oscillator with Self Compensation for Frequency Drift and PVT Corners Variations". 2019.
    10.1109/ICECS.2018.8618027
  3. Granja, R.; Santos, M.; Guilherme, J.; Horta, N.. "11.7b Time-To-Digital Converter with 0.82ps resolution in 130nm CMOS Technology". 2018.
    10.1109/PRIME.2018.8430374
  4. Canelas, A.; Povoa, R.; Martins, R.; Lourenco, N.; Guilherme, J.; Horta, N.. "A 20 DB Gain Two-Stage Low-Noise Amplifier with High Yield for 5 GHz Applications". 2018.
    10.1109/SMACD.2018.8434917
  5. Calvillo, J.; Guilherme, J.; Horta, N.. "Design of a BGR suitable for the space industry with performance of 1.25 v with 0.758 ppm/°C TC from - 55° to 125°C". 2017.
    10.1109/NGCAS.2017.52
  6. Cachaco, J.; Machado, N.; Lourenco, N.; Guilherme, J.; Horta, N.. "Automatic technology migration of analog IC designs using generic cell libraries". 2017.
    10.23919/DATE.2017.7927189
  7. Fitas, A.; Horta, N.; Guilherme, J.. "Design of a radiation-hardened curvature compensated bandgap reference circuit". 2016.
    10.1109/PRIME.2016.7519555
  8. Santos, M.; Horta, N.; Guilherme, J.. "An 8bit logarithmic AD converter Using cross-coupled inverters and a time-to-digital converter". 2016.
    10.1109/PRIME.2016.7519548
  9. Silva, C.; Guilherme, J.; Horta, N.. "SCALES: A high speed simulator tool for pipeline A/D converters". 2016.
    10.1109/SMACD.2016.7520751
  10. Santos, M.; Horta, N.; Guilherme, J.. "Logarithmic AD conversion using latched comparators and a time-to-digital converter". 2015.
    10.1109/ICECS.2014.7049986
  11. Guilherme, D.; Pereira, J.; Horta, N.; Guilherme, J.. "Thermal-aware floorplanning and layout generation of MOSFET power stages". 2015.
    10.1109/ISCAS.2015.7169135
  12. Silva, B.; Horta, N.; Guilherme, J.. "A rad-hard DC-DC converter controller". 2015.
    10.1109/ICECS.2014.7050016
  13. Guilherme, D.; Horta, N.; Guilherme, J.. "Automatic layout generation of power MOSFET transistors in bulk CMOS". 2015.
    10.1109/ICECS.2014.7050058
  14. Ribeiro, A.; Sirgado, A.; Aperta, J.; Lopes, A.; Guilherme, J.; Correia, P.; Pires, G.; Nunes, U.. "A low-cost eeg stand-alone device for brain computer interface". 2009.
  15. Barros, M.; Guilherme, J.; Horta, N.. "Analog circuits and systems optimization based on evolutionary computation techniques". 2008.
  16. Lourenço, N.; Vianello, M.; Guilherme, J.; Horta, N.. "LAYGEN - Automatic layout generation of analog ICs from hierarchical template descriptions". 2006.
  17. Guilherme, J.; Vital, J.; Franca, J.. "A true logarithmic analog-to-digital pipeline converter with 1.5 bit/stage and digital correction". 2001.
  18. Guilherme, J.; Figueiredo, P.; Azevedo, P.; Minderico, G.; Leal, A.; Vital, J.; Franca, J.. "A pipeline 15-b 10-Msample/s analog-to-digital converter for ADSL applications". 2001.
    10.1109/ISCAS.2001.921876
  19. Guilherme, J.; Figueiredo, P.; Azevedo, P.; Minderico, G.; Leal, A.; Vital, J.; Franca, J.. "Design considerations for high resolution pipeline ADCs in digital CMOS technology". 2001.
  20. Guilherme, J.; Vital, J.; Franca, J.. "Performance testing of logarithmic Analogto-digital converters". 2001.
  21. Guilherme, J.; Horta, N.C.; Franca, J.E.. "Symbolic synthesis of non-linear data converters". 1998.
  22. Correia, A.J.; Guilherme, J.C.; Franca, J.E.. "Current-mode algorithmic pipeline analog-to-digital converter". 1996.
  23. Guilherme, Jorge; Franca, Jose E.. "New CMOS logarithmic A/D converters employing pipeline and algorithmic architectures". 1995.
  24. Guilherme, Jorge; Vital, Joao; Franca, Jose E.. "New logarithmic two-step flash A/D converter with digital error correction for MOS technology". 1995.
  25. Guilherme, Jorge; Franca, Jose E.. "Digitally-controlled analogue signal processing and conversion techniques employing a logarithmic building block". 1994.
  26. Guilherme, Jorge; Franca, Jose E.. "Logarithmic digital-analog converter for digital CMOS technology". 1994.
  27. Finco, S.; Guilherme, J.; Behrens, F.H.; Simas, M.I.Castro. "Monolithic smart switching cell targeted to a wide range of low power high density applications". 1994.
Journal article
  1. Antonio Canelas; Ricardo Povoa; Ricardo Martins; Nuno Lourenco; Jorge Guilherme; Joao Paulo Carvalho; Nuno Horta. "FUZYE: A Fuzzy ${c}$ -Means Analog IC Yield Optimization Using Evolutionary-Based Algorithms". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39 1 (2020): 1-13. https://doi.org/10.1109/TCAD.2018.2883978.
    10.1109/TCAD.2018.2883978
  2. Jonathan P. Calvillo; Ricardo Póvoa; Jorge Guilherme; Nuno Horta. "Second-order compensation BGR with low TC and high performance for space applications". Integration 63 (2018): 256-265. https://doi.org/10.1016/j.vlsi.2018.07.001.
    10.1016/j.vlsi.2018.07.001
  3. Guilherme, Jorge. "Logarithmic AD Converter with Selectable Transfer Characteristic". IEEE Transactions on Circuits and Systems II: Express Briefs (2016): http://www.it.pt/Publications/PaperJournal/22660.
    10.1109/TCSII.2015.2503567
  4. Guilherme, Jorge. "A survey on nonlinear analog-to-digital converters". Integration, The VLSI Journal (2014): http://www.it.pt/Publications/PaperJournal/8830.
    10.1016/j.vlsi.2013.06.001
  5. Martins, R.; Lourenço, N.; Rodrigues, S.; Guilherme, J.; Horta, N.. "AIDA: Automated analog IC design flow from circuit level to layout". 2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012 (2012): 29-32. http://www.scopus.com/inward/record.url?eid=2-s2.0-84870608461&partnerID=MN8TOARS.
    10.1109/SMACD.2012.6339409
  6. Silva, C.; Horta, N.; Guilherme, J.; Ayzac, P.. "SCALES - A behavioral simulator for pipelined analog-to-digital converter design". 2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012 (2012): 149-152. http://www.scopus.com/inward/record.url?eid=2-s2.0-84870591041&partnerID=MN8TOARS.
    10.1109/SMACD.2012.6339439
  7. Guilherme, D.; Guilherme, J.; Horta, N.. "Automatic topology selection and sizing of class-D loop-filters for minimizing distortion based on an evolutionary optimization kernel". Analog Integrated Circuits and Signal Processing 73 1 (2012): 21-32. http://www.scopus.com/inward/record.url?eid=2-s2.0-84866732666&partnerID=MN8TOARS.
    10.1007/s10470-011-9716-4
  8. Sousa, P.; Duarte, C.; Barros, M.; Guilherme, J.; Horta, N.. "Optimal OpAmp sizing based on a fuzzy-genetic kernel". Genetic and Evolutionary Computation Conference, GECCO'11 - Companion Publication (2011): 827-828. http://www.scopus.com/inward/record.url?eid=2-s2.0-80051935426&partnerID=MN8TOARS.
    10.1145/2001858.2002109
  9. Cadete, F.; Guilherme, D.; Guilherme, J.; Horta, N.. "Overcurrent detection circuit for integrated class-D amplifiers". 2011 20th European Conference on Circuit Theory and Design, ECCTD 2011 (2011): 401-404. http://www.scopus.com/inward/record.url?eid=2-s2.0-80155201158&partnerID=MN8TOARS.
    10.1109/ECCTD.2011.6043371
  10. Barros, M.F.M.; Guilherme, J.M.C.; Horta, N.C.G.. "Studies in Computational Intelligence: Introduction". Studies in Computational Intelligence 294 (2010): 1-18. http://www.scopus.com/inward/record.url?eid=2-s2.0-77951122662&partnerID=MN8TOARS.
    10.1007/978-3-642-12346-7_1
  11. Guilherme, D.; Guilherme, J.; Horta, N.. "Automatic topology selection and sizing of class-D loop-filters for minimizing distortion". 2010 11th International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design, SM2ACD 2010 (2010): http://www.scopus.com/inward/record.url?eid=2-s2.0-78651517886&partnerID=MN8TOARS.
    10.1109/SM2ACD.2010.5672299
  12. Barros, M.F.M.; Guilherme, J.M.C.; Horta, N.C.G.. "State-of-the-art on analog design automation". Studies in Computational Intelligence 294 (2010): 19-47. http://www.scopus.com/inward/record.url?eid=2-s2.0-77951114130&partnerID=MN8TOARS.
    10.1007/978-3-642-12346-7_2
  13. Barros, M.F.M.; Guilherme, J.M.C.; Horta, N.C.G.. "Evolutionary analog IC design optimization". Studies in Computational Intelligence 294 (2010): 49-88. http://www.scopus.com/inward/record.url?eid=2-s2.0-77951102578&partnerID=MN8TOARS.
    10.1007/978-3-642-12346-7_3
  14. Barros, M.F.M.; Guilherme, J.M.C.; Horta, N.C.G.. "Conclusions". Studies in Computational Intelligence 294 (2010): 187-225. http://www.scopus.com/inward/record.url?eid=2-s2.0-77951099601&partnerID=MN8TOARS.
    10.1007/978-3-642-12346-7_7
  15. Barros, M.F.M.; Guilherme, J.M.C.; Horta, N.C.G.. "Enhanced techniques for analog circuits design using SVM models". Studies in Computational Intelligence 294 (2010): 89-107. http://www.scopus.com/inward/record.url?eid=2-s2.0-77951096168&partnerID=MN8TOARS.
    10.1007/978-3-642-12346-7_4
  16. Barros, M.F.M.; Guilherme, J.M.C.; Horta, N.C.G.. "Optimization of analog circuits and systems - Applications". Studies in Computational Intelligence 294 (2010): 139-186. http://www.scopus.com/inward/record.url?eid=2-s2.0-77951127390&partnerID=MN8TOARS.
    10.1007/978-3-642-12346-7_6
  17. Barros, M.F.M.; Guilherme, J.M.C.; Horta, N.C.G.. "Analog IC design environment architecture". Studies in Computational Intelligence 294 (2010): 109-137. http://www.scopus.com/inward/record.url?eid=2-s2.0-77951121884&partnerID=MN8TOARS.
    10.1007/978-3-642-12346-7_5
  18. Barros, M.; Guilherme, J.; Horta, N.. "Analog circuits optimization based on evolutionary computation techniques". Integration, the VLSI Journal 43 1 (2010): 136-155. http://www.scopus.com/inward/record.url?eid=2-s2.0-70449674085&partnerID=MN8TOARS.
    10.1016/j.vlsi.2009.09.001
  19. Sousa, P.; Duarte, C.; Barros, M.; Guilherme, J.; Horta, N.. "Enhancing analog IC design optimization kernels with simple fuzzy models". ECCTD 2009 - European Conference on Circuit Theory and Design Conference Program (2009): 775-778. http://www.scopus.com/inward/record.url?eid=2-s2.0-71249097406&partnerID=MN8TOARS.
    10.1109/ECCTD.2009.5275099
  20. Lee, J.; Kang, J.; Park, S.; Seo, J.-S.; Anders, J.; Guilherme, J.; Flynn, M.P.. "A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s logarithmic pipeline ADC". IEEE Journal of Solid-State Circuits 44 10 (2009): 2755-2765. http://www.scopus.com/inward/record.url?eid=2-s2.0-70350578839&partnerID=MN8TOARS.
    10.1109/JSSC.2009.2028052
  21. Silva, A.; Guilherme, J.; Horta, N.. "Reconfigurable multi-mode sigma-delta modulator for 4G mobile terminals". Integration, the VLSI Journal 42 1 (2009): 34-46. http://www.scopus.com/inward/record.url?eid=2-s2.0-56349118361&partnerID=MN8TOARS.
    10.1016/j.vlsi.2008.07.004
  22. Silva, A.; Horta, N.; Guilherme, J.. "A reconfigurable A/D converter for 4G wireless systems". Proceedings - IEEE International Symposium on Circuits and Systems (2008): 924-927. http://www.scopus.com/inward/record.url?eid=2-s2.0-51749117159&partnerID=MN8TOARS.
    10.1109/ISCAS.2008.4541570
  23. Santos, M.; Pires, C.; Guilherme, J.; Horta, N.. "Overview of radiation effects and design constraints off fully custom SMPS". IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS (2008): 372-375. http://www.scopus.com/inward/record.url?eid=2-s2.0-62949208052&partnerID=MN8TOARS.
    10.1109/APCCAS.2008.4746037
  24. Silva, A.; Horta, N.; Guilherme, J.. "Design of a multimode reconfigurable sigma-delta converter for 4G wireless receivers". European Conference on Circuit Theory and Design 2007, ECCTD 2007 (2008): 132-135. http://www.scopus.com/inward/record.url?eid=2-s2.0-49749119980&partnerID=MN8TOARS.
    10.1109/ECCTD.2007.4529554
  25. Barros, M.; Guilherme, J.; Horta, N.. "An evolutionary optimization kernel using a dynamic GA-SVM model applied to analog IC design". European Conference on Circuit Theory and Design 2007, ECCTD 2007 (2008): 32-35. http://www.scopus.com/inward/record.url?eid=2-s2.0-49749096008&partnerID=MN8TOARS.
    10.1109/ECCTD.2007.4529529
  26. Barros, M.; Guilherme, J.; Horta, N.. "GA-SVM feasibility model and optimization kernel applied to analog IC design automation". Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI (2007): 469-472. http://www.scopus.com/inward/record.url?eid=2-s2.0-34748865083&partnerID=MN8TOARS.
    10.1145/1228784.1228895
  27. Barros, M.; Guilherme, J.; Horta, N.. "GA-SVM optimization kernel applied to analog IC design automation". Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems (2006): 486-489. http://www.scopus.com/inward/record.url?eid=2-s2.0-47349100706&partnerID=MN8TOARS.
    10.1109/ICECS.2006.379831
  28. Barros, M.; Neves, G.; Guilherme, J.; Horta, N.. "An evolutionary optimization kernel with adaptive parameters applied to analog circuit design". ISSCS 2005: International Symposium on Signals, Circuits and Systems - Proceedings 2 (2005): 545-548. http://www.scopus.com/inward/record.url?eid=2-s2.0-33749060382&partnerID=MN8TOARS.
    10.1109/ISSCS.2005.1511298
  29. Neves, G.; Barros, M.; Guilherme, J.; Horta, N.. "Design automation methodology for analog IC design matching designers approach". ISSCS 2005: International Symposium on Signals, Circuits and Systems - Proceedings 2 (2005): 549-552. http://www.scopus.com/inward/record.url?eid=2-s2.0-33749053098&partnerID=MN8TOARS.
    10.1109/ISSCS.2005.1511299
  30. Guilherme, J.; Vital, J.; Franca, J.. "A CMOS logarithmic pipeline A/D converter with a dynamic range of 80 dB". Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems 1 (2002): 193-196. http://www.scopus.com/inward/record.url?eid=2-s2.0-1242316762&partnerID=MN8TOARS.
    10.1109/ICECS.2002.1045366
  31. Guilherme, Jorge. "A CMOS Analog-Digital Audio Processor for a Portable Radiotelephone". IEEE Journal of Solid-State Circuits (1993): http://www.it.pt/Publications/PaperJournal/1227.
  32. Guilherme, J.; Vital, J.C.; Franca, J.E.. "A CMOS Analog-Digital Audio Processor for a Portable Radiotelephone". IEEE Journal of Solid-State Circuits 28 5 (1993): 560-568. http://www.scopus.com/inward/record.url?eid=2-s2.0-0027592898&partnerID=MN8TOARS.
    10.1109/4.229399

Intellectual property

Patent
  1. Guilherme, Jorge. 2017. "CONVERSOR ANALÓGICO-DIGITAL COM CARACTERÍSTICA DE TRANSFERÊNCIA LOGARÍTMICA". Portugal.
    Granted/Issued
  2. Guilherme, Jorge. 2013. "CONVERSOR ANALÓGICO-DIGITAL COM CARACTERÍSTICA DE TRANSFERÊNCIA LOGARÍTMICA". Portugal.
Provisional application for patent
  1. 2020. "MÉTODO DE CONVERSÃO ANALÓGICO-DIGITAL COM CARACTERÍSTICA DE TRANSFERÊNCIA LOGARÍTMICA E CALIBRAÇÃO PARA SINAIS DIFERENCIAIS BIPOLARES".
    Disclosed
Activities

Journal scientific committee

Journal title (ISSN) Publisher
2017/05/01 - Current AEÜ - International Journal of Electronics and Communications (1434-8411) Elsevier
Distinctions

Award

2017 Silver Leaf Award, Silver Leaf Award for Design of a BGR suitable for The Space Industry with Performance of 1.25 V with 0.758 ppm/°C TC from - 55° to 125°C
IEEE Circuits and Systems Society, United States
2016 Winner of EDA Competition Award” The 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design
IEEE, United States
2010 Best Student Paper Award - SM2ACD
IEEE, United States

Title

2015 Senior Member IEEE
IEEE, United States

Other distinction

2012 Honorable Mention from SMACD 2012 Competition on Analog IC Design Automation - SMACD
IEEE, United States