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Diogo Marques concluded the Integrated Master in Electrical and Computer Engineering in 2017 at Instituto Superior Técnico. Currently, the research interests of Diogo Marques are focused on the area of computer architectures, in particular in modern multicore general-purpose processors. He is currently performing his research in the High-Performance Computing Architectures and Systems (HPCAS) at INESC-ID, in the scope of his PhD Thesis. This investigation is focused on insightful modeling of modern multi-core processors for performance, power and energy-efficiency, based on the Cache-Aware Roofline Model.
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Identification

Personal identification

Full name
Diogo Marques

Citation names

  • Marques, Diogo

Author identifiers

Ciência ID
4712-7A3D-2F18
ORCID iD
0000-0002-8294-3306

Email addresses

  • diogo.marques@inesc-id.pt (Professional)

Knowledge fields

  • Engineering and Technology - Electrotechnical Engineering, Electronics and Informatics - Computer Hardware and Architecture

Languages

Language Speaking Reading Writing Listening Peer-review
English Upper intermediate (B2) Upper intermediate (B2) Upper intermediate (B2) Intermediate (B1) Upper intermediate (B2)
Portuguese (Mother tongue)
Education
Degree Classification
2012/09/12 - 2017/11/21
Concluded
 Engenharia Electrotécnica e de Computadores (Mestrado integrado)
Major in Electrónica e Computadores
Universidade de Lisboa Instituto Superior Técnico, Portugal
"Performance and Energy-Efficiency Modelling for Multi-Core Processors" (THESIS/DISSERTATION)
 17
Affiliation

Science

Category
Host institution 		Employer
2016/09 - 2018/12 Research Trainee (Research) Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal

Others

Category
Host institution 		Employer
2016/07/01 - 2016/08/01 Discover Summer Internship - Unified Comms Product Development - Development of 100 automatic tests using the program Device Anywhere in order to improve the testing and debugging of a tool. Vodafone Portugal, Portugal
Projects

Contract

Designation Funders
2018/06/01 - 2021 HiPerBio: "High Performance and Energy-efficient Processing of Bioinformatic Applications on Emergent Heterogeneous Systems"
PTDC/CCICOM/31901/2017
Researcher
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia
Ongoing
2018/07 - 2020/12 IntelCARM: "Boosting the roofline-based optimization guidance and performance modeling for modern CPU systems"
N/a
Researcher
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Intel Corp
Concluded
Outputs

Publications

Conference abstract
  1. Marques, Diogo; Duarte, Helder; Sousa, Leonel; Ilic, Aleksandar. "Analyzing Performance of Multi-cores and Applications with Cache-aware Roofline Model". Paper presented in Special Session on High Performance Computing for Application Benchmarking and Optimization, International Conference on High Performance Computing & Simulation, Genova, 2017.
    Published • 10.1109/hpcs.2017.158
Conference paper
  1. Diogo Marques; Rafael Campos; Sergio Santander-Jiménez; Zakhar Matveev; Leonel Sousa; Aleksandar Ilic. "Unlocking Personalized Healthcare on Modern CPUs/GPUs: Three-way Gene Interaction Study". Paper presented in IEEE International Parallel & Distributed Processing Symposium, Lyon, 2022.
    Accepted
  2. Campos, Rafael; Marques, Diogo; Santander-Jiménez, Sergio; Sousa, Leonel; Ilic, Aleksandar. "Heterogeneous CPU+iGPU Processing for Efficient Epistasis Detection". Paper presented in International European Conference on Parallel and Distributed Computing (EuroPar), Warsaw, 2020.
    Published • 10.1007/978-3-030-57675-2_38
  3. Marques, Diogo; Duarte, Helder; Ilic, Aleksandar; Sousa, Leonel; Belenov, Roman; Thierry, Philippe; Matveev, Zakhar A.. "Performance Analysis with Cache-Aware Roofline Model in Intel Advisor". Paper presented in International Conference on High Performance Computing & Simulation, Genova, 2017.
    Published • 10.1109/hpcs.2017.150
Journal article
  1. Marques, Diogo; Ilic, Aleksandar; Sousa, Leonel. "Mansard Roofline Model: Reinforcing the Accuracy of the Roofs". ACM Transactions on Modeling and Performance Evaluation of Computing Systems 6 2 (2021): 1-23. http://dx.doi.org/10.1145/3475866.
    Published • 10.1145/3475866
  2. Marques, Diogo; Ilic, Aleksandar; Matveev, Zakhar A.; Sousa, Leonel. "Application-driven Cache-Aware Roofline Model". Future Generation Computer Systems 107 (2020): 257-273. http://dx.doi.org/10.1016/j.future.2020.01.044.
    Published • 10.1016/j.future.2020.01.044
Activities

Oral presentation

Presentation title Event name
Host (Event location)
2020/11 Aleksandar Ilic, Diogo Marques, Rafael Campos, Sergio Santander-Jiménez, Leonel Sousa. Cache-Aware Roofline Model: Performance, Power and Energy-Efficiency, in Intel eXtreme Performance User Group conference (IXPUG), Tutorial, virtual event, October 2020. Intel eXtreme Performance User Group conference (IXPUG)
2020/11 Aleksandar Ilic, Diogo Marques, Rafael Campos, Sergio Santander-Jiménez, Ricardo Nobre, Leonel Sousa. Rooflining Bioinformatics: Boosting Epistasis Detection with Cache-aware Roofline Model, in Intel oneAPI Developer Summit, virtual event, November 2020. Intel oneAPI Developer Summit
2020/11 Samuel W. Williams, Aleksandar Ilic, Diogo Marques, Zakhar Matveev, Max Katz, JaeHyuk Kwack, Charlene Yang, Colleen Bertoni, Khaled Ibrahim (in collaboration with Intel®, NVIDIA and LBNL). Performance Tuning with the Roofline Model on GPUs and CPUs, in International Conference for High Performance Computing, Networking, Storage and Analysis (SC), Tutorial, virtual event, November 2020. International Conference for High Performance Computing, Networking, Storage and Analysis (SC)
2019/06 Charlene Yang, Zakhar Matveev, Aleksandar Ilic, Leonel Sousa and Diogo Marques (in collaboration with Intel® and LBNL). Performance Optimization of Scientific Codes with the Roofline Model, in ISC High Performance 2019 (ISC-HPC), Tutorial, Frankfurt, Germany, June 2019. ISC High Performance
(Frankfurt, Germany)
2019/06 Diogo Marques, Aleksandar Ilic, Leonel Sousa and Zakhar Matveev (in collaboration with Intel®). Roofline Model Based Optimization Guidance and Tuning for Modern CPUs, in Intel® Developer Connect , Tutorial, Frankfurt, Germany, June 2019. Intel® Developer Connect
(Frankfurt, Germany)
2017/11 Tuomas S. Koskela, Aleksandar Ilic, Zakhar A. Matveev, Samuel W. Williams and Philippe Thierry (in collaboration with Intel® and LBNL). Performance Tuning of Scientific Codes with the Roofline Model, in International Conference for High Performance Computing, Networking, Storage and Analysis (SC), Tutorial, Denver, CO, USA, November 2017. Tutorial Session: "Performance analysis with Intel Advisor and Cache-Aware Roofline Model: Minighost Optimization Example" by Diogo Marques, Aleksandar Ilic, Roman Belenov, Phillipe Thierry and Zakhar Matveev. International Conference for High Performance Computing, Networking, Storage and Analysis
(Denver, United States)
2017/11 Carlos Rosales, Dmitry Prohorov, Zakhar Matveev, and Aleksandar Ilic. Tuning for the Intel® Xeon® Scalable Processor (Code Named Skylake), in Intel® HPC Developer Conference, Tutorial, Denver, CO, USA, November 2017. (in collaboration with Intel®). Tutorial Session: "Performance Analysis with Intel Advisor and Cache-aware Roofline Model: Toypush Optimization Example", Diogo Marques, Aleksandar Ilic, Frederico Pratas, Leonel Sousa, Phillipe Thierry and Zakhar Matveev. Intel® HPC Developer Conference
(Denver, United States)
2017/07 Diogo Marques, Helder Duarte, Leonel Sousa and Aleksandar Ilic. Analyzing Performance of Multi-cores and Applications with Cache-aware Roofline Model, in Special Session on High Performance Computing for Application Benchmarking and Optimization (HPBench'17), International Conference on High Performance Computing & Simulation (HPCS'17), Genoa, Italy, July 2017. url: HPCS'17 | invited talk. Special Session on High Performance Computing for Application Benchmarking and Optimization, International Conference on High Performance Computing & Simulation
(Genoa, Italy)

Conference scientific committee

Conference name Conference host
2020 - 2020 International European Conference on Parallel and Distributed Computing Warsaw, Poland
2020 - 2020 International Conference on Architecture of Computing Systems Aachen, Germany
2020 - 2020 International Workshop on Job Scheduling Strategies for Parallel Processing New Orleans, Louisiana, USA
2020 - 2020 IEEE Cluster Kobe, Japan
2019 - 2019 International Symposium on Circuits and Systems Sapporo, Hokkaido, Japan
2019 - 2019 International Workshop on Data Locality Göttingen, Germany
2019 - 2019 International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms
2019 - 2019 Special Session on High Performance Computing for Application Benchmarking and Optimization Dublin, Ireland
2019 - 2019 International Conference on High Performance Computing & Simulation Dublin, Ireland
2019 - 2019 International Conference on Acoustics, Speech, and Signal Processing Brighton, UK
2019 - 2019 International Conference on Parallel Processing Kyoto, Japan
2019 - 2019 INForum - Simpósio de Informática Lisbon, Portugal
2019 - 2019 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation Samos, Greece
2018 - 2018 International European Conference on Parallel and Distributed Computing Turin, Italy
2018 - 2018 Special Session on High Performance Computing for Application Benchmarking and Optimization Orléans, France
2018 - 2018 International Conference on High Performance Computing & Simulation Orléans, France
2018 - 2018 International Midwest Symposium on Circuits and Systems Dallas, Texas, USA
2018 - 2018 International Symposium on Computer Architecture and High Performance Computing Lyon, France
2018 - 2018 International Workshop on Data Locality Turin, Italy
2018 - 2018 Artifact Evaluation for International Conference on Parallel Architectures and Compilation Techniques Limassol, Cyprus
2017 - 2017 International Workshop on Job Scheduling Strategies for Parallel Processing Orlando, USA
2017 - 2017 International Workshop on Data Locality Santiago de Compostela, Spain
2017 - 2017 International Conference on High Performance Computing, Data and Analytics Jaipur, India
2017 - 2017 International Conference On Parallel Processing And Applied Mathematics Lublin, Poland
2017 - 2017 International Symposium on Computer Architecture and High Performance Computing Campinas, Brasil
2017 - 2017 Special Session on High Performance Computing for Application Benchmarking and Optimization Genoa, Italy

Journal scientific committee

Journal title (ISSN) Publisher
2020 - 2020 Computing in Science and Engineering (1521-9615) IEEE Computer Society
2019 - 2019 ACM Transactions on Architecture and Code Optimization (1544-3973) Association for Computing Machinery
2018 - 2019 Concurrency and Computation Practice and Experience (1532-0634) Wiley (John Wiley & Sons)
2018 - 2018 ACM Transactions on Embedded Computing Systems (1558-3465) Association for Computing Machinery
Distinctions

Other distinction

2017 Academic Merit Board - Diploma of Academic Excellence
Universidade de Lisboa Instituto Superior Técnico, Portugal
2016 Academic Merit Board - Diploma of Academic Excellence
Universidade de Lisboa Instituto Superior Técnico, Portugal
2015 Academic Merit Board - Diploma of Academic Excellence
Universidade de Lisboa Instituto Superior Técnico, Portugal
2014 Academic Merit Board
Universidade de Lisboa Instituto Superior Técnico, Portugal
2013 Academic Merit Board
Universidade de Lisboa Instituto Superior Técnico, Portugal