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João Dias Lopes concluded the Master of Science in Electrical and Computer Engineering in 2017/11/21 by Universidade de Lisboa, at Instituto Superior Técnico and the Bachelor of Science in Electrical and Computer Engineering in 2016/07/01 by Universidade de Lisboa, at Instituto Superior Técnico. Has 1 journal paper, 1 book chapter and several conference papers. Participates as Research Fellow in Power Efficiency and Performance for Embedded and HPC Systems with Custom CGRAs (PEPCC) project. Works in the areas of Engineering and Technology - Electrotechnical Engineering, Electronics and Informatics - Computer Hardware and Architecture on Digital circuits design for embedded and low power systems and Microelectronics. In his curriculum Ciência Vitae the most frequent terms in the context of scientific, technological and artistic-cultural output are: Reconfigurable Computing; Coarse-Grained Reconfigurable Arrays; Embedded Systems; Power-efficient Computing; High-performance Computing.
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Identification

Personal identification

Full name
João Dias Lopes

Author identifiers

Ciência ID
8E19-37E3-AF01

Knowledge fields

  • Engineering and Technology - Electrotechnical Engineering, Electronics and Informatics - Computer Hardware and Architecture
  • Engineering and Technology - Electrotechnical Engineering, Electronics and Informatics - Electrical and Electronic Engineering

Languages

Language Speaking Reading Writing Listening Peer-review
Portuguese (Mother tongue)
English Upper intermediate (B2) Advanced (C1) Upper intermediate (B2) Upper intermediate (B2)
Education
Degree Classification
2014/09/08 - 2017/11/21
Concluded
 Electrical and Computer Engineering (Mestrado)
Major in Hardware and software design for embedded systems
Universidade de Lisboa Instituto Superior Técnico, Portugal
"VERSAT, a Compile-Friendly Reconfigurable Processor - Architecture" (THESIS/DISSERTATION)
 15
2009/09/14 - 2016/07/01
Concluded
 Electrical and Computer Engineering (Licenciatura)
Universidade de Lisboa Instituto Superior Técnico, Portugal
 12
Affiliation

Science

Category
Host institution 		Employer
2014/07/04 - 2018/03/16 Research Trainee (Research) Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
Projects

Contract

Designation Funders
2020/01/15 - Current Power Efficiency and Performance for Embedded and HPC Systems with Custom CGRAs
PTDC/EEI-HAC/30848/2017
Research Fellow
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia
Ongoing
Outputs

Publications

Book chapter
  1. Lopes, João D.; de Sousa, José T.. "Versat, a Minimal Coarse-Grain Reconfigurable Array". In High Performance Computing for Computational Science – VECPAR 2016, 174-187. Springer International Publishing, 2017.
    10.1007/978-3-319-61982-8_17
Conference paper
  1. Santiago, Rui; D. Lopes, João; T. de Sousa, José. "Compiler for the Versat reconfigurable architecture". Paper presented in XIII Jornadas sobre Sistemas Reconfiguráveis, Aveiro, 2017.
    Published • 10.5281/ZENODO.3685537
  2. D. Lopes, João; T. de Sousa, José. "Versat, a Minimal Coarse-Grain Reconfigurable Array". Paper presented in 12th International Meeting on High Performance Computing for Computational Science (VECPAR), Porto, 2016.
    Published
Conference poster
  1. Mário, Valter; D. Lopes, João; Véstias, Mário; T. de Sousa, José. "Implementing CNNs using a Linear Array of Full Mesh CGRAs". Paper presented in 16th International Symposium on Applied Reconfigurable Computing, 2020.
  2. Paulino, Nuno; Canas Ferreira, João; M. P. Cardoso, João; D. Lopes, João; Véstias, Mário; T. Sousa, José. "Power Efficiency and Performance for Embedded and HPC Systems with Custom CGRAs". Paper presented in Design, Automation and Test in Europe Conference, 2020.
  3. Lopes, Joao D.; de Sousa, Jose T.; Neto, Horacio; Vestias, Mario. "K-means clustering on CGRA". Paper presented in 27th International Conference on Field-Programmable Logic and Applications, 2017.
    10.23919/fpl.2017.8056854
Journal article
  1. João D. Lopes; Mário P. Véstias; Rui Policarpo Duarte ; Horácio C. Neto; José T. de Sousa . "Coarse-Grained Reconfigurable Computing with the Versat Architecture". Electronics 10 6 (2021): 669-669. https://doi.org/10.3390/electronics10060669.
    10.3390/electronics10060669
Online resource
  1. D. Lopes, João; T. de Sousa, José. Fast Fourier Transform on the Versat CGRA. 2017. https://zenodo.org/record/3685577.
    10.5281/ZENODO.3685577
  2. Santiago, Rui; D. Lopes, João; T. de Sousa, José. Versat, a Runtime Partially Reconfigurable Coarse-Grain Reconfigurable Array using a Programmable Controller. 2016. https://zenodo.org/record/3685610.
    10.5281/ZENODO.3685610