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Rui Duarte. Holds a Doctor of Philosophy (PhD) in Electrical and Electronic Engineering in 2014/05/01 by Imperial College London, UK. He completed the Mestrado in Mestrado em Engenharia Electrotécnica e de Computadores in 2008 by Universidade de Lisboa Instituto Superior Técnico, Licenciatura in Licenciatura em Engenharia de Sistemas das Telecomunicações e Electrónica in 2005 by Instituto Politécnico de Lisboa Instituto Superior de Engenharia de Lisboa, Bacharelato in Bacharelato em Engenharia de Sistemas das Telecomunicações e Electrónica in 2003 by Instituto Politécnico de Lisboa Instituto Superior de Engenharia de Lisboa. Is a lecturer in Instituto Politécnico de Lisboa Instituto Superior de Engenharia de Lisboa (ISEL/IPL) and Researcher in Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa (INESC-ID/INOV-LAB). Published 16 articles in journals. Has 4 section(s) of books and 4 book(s). Has 1 patent(s) registered. Organized 6 event(s). Supervised 2 PhD thesis(es). Supervised 13 MSc dissertation(s) e co-supervised 2. Has received 10 awards and/or honors. Participates and/or participated as Post-doc Fellow in 1 project(s), Principal investigator in 2 project(s), Research Fellow in 1 project(s), Researcher in 3 project(s) and Technical development in 1 project(s). Works in the area(s) of Engineering and Technology with emphasis on Electrotechnical Engineering, Electronics and Informatics with emphasis on Computer Hardware and Architecture, Engineering and Technology with emphasis on Electrotechnical Engineering, Electronics and Informatics with emphasis on Electrical and Electronic Engineering and Exact Sciences with emphasis on Computer and Information Sciences with emphasis on Computer Sciences. In their professional activities interacted with 82 collaborator(s) co-authorship of scientific papers.
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Identification

Personal identification

Full name
Rui Duarte

Citation names

  • Rui Policarpo Duarte

Author identifiers

Ciência ID
B91E-770F-19A3
ORCID iD
0000-0002-7060-4745
Google Scholar ID
3gdRS_0AAAAJ
Researcher Id
I-4402-2015
Scopus Author Id
24823991600

Knowledge fields

  • Engineering and Technology - Electrotechnical Engineering, Electronics and Informatics - Computer Hardware and Architecture
  • Engineering and Technology - Electrotechnical Engineering, Electronics and Informatics - Electrical and Electronic Engineering
  • Exact Sciences - Computer and Information Sciences - Computer Sciences
Education
Degree Classification
2015
Concluded
 Curso de Gestão de Projectos de Engenharia (PMP-PMBOK) (Outros)
Universidade de Lisboa, Portugal
 n/a
2009/10/01 - 2014/05/01
Concluded
 PhD in Electrical and Electronic Engineering (Doctor of Philosophy)
Major in Electrical and Electronic Engineering
Imperial College London, United Kingdom
"Variation-Aware High-Level DSP Circuit Design Optimization Framework for FPGAs" (THESIS/DISSERTATION)
 N/A
2005 - 2008
Concluded
 Mestrado em Engenharia Electrotécnica e de Computadores (Mestrado)
Major in Engenharia Electrotécncia e de Computadores
Universidade de Lisboa Instituto Superior Técnico, Portugal
"Reconfigurable Hardware for Scientific Computing: High-performance system to compute Gauss-Jordan elimination with partial pivoting" (THESIS/DISSERTATION)
2003 - 2005
Concluded
 Licenciatura em Engenharia de Sistemas das Telecomunicações e Electrónica (Licenciatura)
Instituto Politécnico de Lisboa Instituto Superior de Engenharia de Lisboa, Portugal
"Interface de Terminal Telefónico Analógico para Sistemas de Comunicação Digital" (THESIS/DISSERTATION)
1999 - 2003
Concluded
 Bacharelato em Engenharia de Sistemas das Telecomunicações e Electrónica (Bacharelato)
Instituto Politécnico de Lisboa Instituto Superior de Engenharia de Lisboa, Portugal
"Conversor Áudio Digital-Analógico para Leitor de CDs / Digital do Analog Audio Converter for CD Player (-112dB noise)" (THESIS/DISSERTATION)
Affiliation

Science

Category
Host institution 		Employer
2015/01/01 - Current Researcher (Research) Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
2014/08/01 - 2014/12/01 Researcher (Research) Universidade de Coimbra Instituto de Sistemas e Robótica, Portugal
Universidade de Coimbra Instituto de Sistemas e Robótica, Portugal
2010 - 2011 Auxiliary Researcher (Research) Imperial College London Department of Electrical and Electronic Engineering, United Kingdom
Imperial College London Department of Electrical and Electronic Engineering, United Kingdom
2006/10/01 - 2008/06/01 Researcher (Research) Instituto de Telecomunicações, Portugal

Teaching in Higher Education

Category
Host institution 		Employer
2022/09/01 - Current Adjunct Teacher (Polytechnic Teacher) Instituto Politécnico de Lisboa Instituto Superior de Engenharia de Lisboa, Portugal
Instituto Politécnico de Lisboa Instituto Superior de Engenharia de Lisboa, Portugal
2016/09/01 - 2019/03/31 Invited Assistant Professor (University Teacher) Universidade de Lisboa Instituto Superior Técnico, Portugal
2016/03/01 - 2017 Invited Adjunct Teacher (Polytechnic Teacher) Instituto Politécnico de Lisboa, Portugal
2015/03/01 - 2016/08/01 Assistant Professor (University Teacher) Universidade Autónoma de Lisboa Departamento de Ciências e Tecnologias, Portugal
2015 - 2016 Assistant Professor (University Teacher) Universidade Autónoma de Lisboa, Portugal
2015 - 2016 Assistant Professor (University Teacher) Universidade Autónoma de Lisboa, Portugal
2009/10/01 - 2014/05/01 Tutor (University Teacher) Imperial College London Department of Electrical and Electronic Engineering, United Kingdom
2005/09/01 - 2009/03/01 Tutor (University Teacher) Universidade de Lisboa Instituto Superior Técnico, Portugal
2008/03/01 - 2008/10/01 Assistant Professor (University Teacher) Universidade Autónoma de Lisboa, Portugal

Positions / Appointments

Category
Host institution 		Employer
2018 - 2018 Chief Hardware Officer Emotai, Hong Kong SAR China
brinc.io, Hong Kong SAR China

Others

Category
Host institution 		Employer
2021/09/01 - 2022/08/30 Managing Director Celestia Portugal, Portugal
Celestia Portugal, Portugal
2015/02/01 - 2016/08/01 Senior electronics engineer and project manager. Design and development of electronic systems and software for real-time embedded systems for heart-rate measurements and applications. Also acted as me Cardio-ID Technologies, Portugal
2009/06/01 - 2009/09/01 Software development for the Galileo Ground Segment, for a real-time distributed system using RTOS Skysoft, Portugal
Skysoft, Portugal
2009/04/01 - 2009/07/01 Telecommunications and Electrical Engineer - responsible for commissioning of DVB-T Broadcasting sites for Portugal Telecom, site survey, remote management, RF and power solutions Emicompor Lda, Portugal
Emicompor Lda, Portugal
2008/01/01 - 2008/10/01 Co-Founder - Management, electronic and telecommunication systems design and development ETConcept, Lda, Portugal
ETConcept, Lda, Portugal
2001/10/01 - 2004/05/01 Electrical and Communications Engineer - Electronic embedded circuit design (hardware e software C++). Dynasys, Portugal
Dynasys, Portugal
Projects

Grant

Designation Funders
2018 - 2020 REVER: Mission System improvement for CAMELOT
31/SI/2017 - I&DT Empresarial (Copromoção)
Researcher
Universidade de Lisboa Instituto Superior Técnico, Portugal
 Agência Nacional de Inovação SA
Cancelled
2010 - 2010 Novo-G
Novo-G
Researcher
Imperial College London Department of Electrical and Electronic Engineering, United Kingdom
Concluded
2005 - 2006 Infra-red Illuminator for license plate recognition
ALPR
Technical development
Instituto Politécnico de Lisboa Instituto Superior de Engenharia de Lisboa, Portugal
 Brisa
Concluded

Contract

Designation Funders
2020/01 - 2022/12 Mommertz
Mommertz1
Principal investigator
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Mommertz GmbH
Ongoing
2018/10/01 - 2022/09/30 Synthetic Aperture Radar Robust Reconfigurable Optimized Computing Architecture
PTDC/EEI-HAC/31819/2017
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia
Concluded
2019/01/01 - 2019/12/31 Instituto de Engenharia de Sistemas e Computadores, Investigação e Desenvolvimento em Lisboa
UID/CEC/50021/2019
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia
Concluded
2018/04/06 - 2019/04/17 Emotai
n/a
Principal investigator
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Emotai
Concluded
2014/06/01 - 2014/12/31 Bottom-up Approaches to Machines dedicated to Bayesian Inference
info:eu-repo/grantAgreement/EC/FP7/618024/EU
Post-doc Fellow
Universidade de Coimbra Departamento de Engenharia Electrotécnica e de Computadores, Portugal
 European Commission
2011/07/01 - 2014/06/30 VARIATION -AWARE HIGH-LEVEL DSP CIRCUIT DESIGN OPTIMISATION FRAMEWORK FOR FPGAS
SFRH/BD/69587/2010
Imperial College London, United Kingdom
 Fundação para a Ciência e a Tecnologia
Concluded
2014 - 2014 DeSyRe - on-Demand System Reliability
287611
Researcher
Imperial College London Department of Electrical and Electronic Engineering, United Kingdom
 European Union
Concluded
2006 - 2008 Top
TOP
Research Fellow
European Space Agency, France
 European Space Agency
Concluded
Outputs

Publications

Book
  1. Duarte, R.P.; Bouganis, C.-S.. Variation-aware optimisation for reconfigurable cyber-physical systems. 2016.
    10.1007/978-3-319-31165-4_24
  2. Lourenço, A.; Alves, A.P.; Carreiras, C.; Duarte, R.P.; Fred, A.. CardioWheel: ECG biometrics on the steering wheel. 2015.
    10.1007/978-3-319-23461-8_27
  3. Duarte, R.P.; Bouganis, C.-S.. A Unified framework for over-clocking linear projections on FPGAs under PVT variation. 2014.
    10.1007/978-3-319-05960-0_5
  4. Silva, V.; Duarte, R.; Véstias, M.; Neto, H.. Multiplier-based double precision floating point divider according to the IEEE-754 standard. 2008.
    10.1007/978-3-540-78610-8_26
Book chapter
  1. Duarte, Rui P.; Cruz, Helena; Neto, Horácio. "Reconfigurable Accelerator for On-Board SAR Imaging Using the Backprojection Algorithm". In Applied Reconfigurable Computing. Architectures, Tools, and Applications, 392-401. Springer International Publishing, 2020.
    Published • 10.1007/978-3-030-44534-8_29
  2. Duarte, Rui P.; Cruz, Helena; Neto, Horácio. "Correction to: Reconfigurable Accelerator for On-Board SAR Imaging Using the Backprojection Algorithm". In Applied Reconfigurable Computing. Architectures, Tools, and Applications, C1-C1. Springer International Publishing, 2020.
    Published • 10.1007/978-3-030-44534-8_30
  3. Helena Cruz; Rui Policarpo Duarte; Horácio Neto. "Fault-Tolerant Architecture for On-board Dual-Core Synthetic-Aperture Radar Imaging". 3-16. Springer International Publishing, 2019.
    10.1007/978-3-030-17227-5_1
  4. Duarte, Rui Policarpo; Bouganis, Christos-Savvas; Duarte, R.P.; Bouganis, C.-S.. "Zero-Latency Datapath Error Correction Framework for Over-Clocking DSP Applications on FPGAs". 2014.
    10.1109/ReConFig.2014.7032566
Conference abstract
  1. Duarte, Rui. "Pushing the performance boundary of linear projection designs through device specific optimisations". 2014.
    10.1145/2554688.2554717
Conference paper
  1. Rui Policarpo Duarte; Duarte Galvão; Cláudio de Campos Neto, Horácio; Mário P. Véstias. "SpaceCANvas: A low-cost open-source CAN-based hardware and software framework for space systems networks". Paper presented in Small Satellites Systems and Services Symposium, Vilamoura, 2022.
    Published
  2. Rui Policarpo Duarte. "Open-Source Framework for Implementation of ECSS-E-ST-50-15C Compliant CAN Bus for Space Systems". Paper presented in 13th IAA Symposium on Small Satellites for Earth Observation, Bermin, 2021.
  3. Rui Policarpo Duarte. "FPGA-Based Traffic-Sign Classification using CNNs". Paper presented in XVI Jornadas Sobre Sistemas Reconfiguráveis (REC 2020), Lisboa, 2020.
  4. Rui Policarpo Duarte. "Redes Neuronais Convolucionais em FPGA de Baixa Densidade". Paper presented in XVI Jornadas Sobre Sistemas Reconfiguráveis (REC 2020), Lisbon, 2020.
  5. Rui Policarpo Duarte. "On-Board Multi-Core Fault Tolerant SAR Imaging Architecture". Paper presented in XV Jornadas Sobre Sistemas Reconfiguráveis (REC 2019), Guimarães, 2019.
  6. Fiolhais, L.; Gonçalves, F.; Duarte, R.P.; Véstias, M.; De Sousa, J.T.. "Low energy heterogeneous computing with multiple RISC-V and CGRA cores". 2019.
    10.1109/ISCAS.2019.8702538
  7. Duarte, R.P.; Neto, H.C.. "Stochastic Processors on FPGAS to Compute Sensor Data Towards Fault-Tolerant IoT Systems". 2019.
    10.1109/DESEC.2018.8625153
  8. Véstias, Mário; Duarte, Rui Policarpo; De Sousa, Jose; Cláudio de Campos Neto, Horácio; Vestias, M.P.; Duarte, R.P.; De Sousa, J.T.; Neto, H.. "Hybrid dot-product calculation for convolutional neural networks in FPGA". 2019.
    10.1109/FPL.2019.00062
  9. Rui Policarpo Duarte. "Biclustering on FPGAs". Paper presented in XIV Workshop on Reconfigurable Systems (REC 2018), Caparica, 2018.
  10. Rui Policarpo Duarte. "CNN-Based Traffic-Sign Detection on FPGAs". Paper presented in XIV Workshop on Reconfigurable Systems (REC 2018), Caparica, 2018.
  11. Rui Policarpo Duarte. "Implementação Eficiente de Múltiplos Produtos Internos com DSP". Paper presented in XIV Workshop on Reconfigurable Systems (REC 2018), Lisbon, 2018.
  12. Vestias, M.; Policarpo Duarte, R.; De Sousa, J.T.; Neto, H.C.; Véstias, Mário Pereira; Duarte, Rui Policarpo; Sousa, José T. de; Neto, Horácio. "Lite-CNN: A high-performance architecture to execute CNNs in low density FPGAs". 2018.
    10.1109/FPL.2018.00075
  13. Nascimento, J.M.P.; V'Estias, M.; Duarte, R.. "Hyperspectral compressive sensing: A low-power consumption approach". 2018.
    10.1117/12.2326118
  14. Duarte, R.P.; Simes, L.; Henriques, R.; Neto, H.C.. "FPGA-based OpenCL accelerator for discovering temporal patterns in gene expression data using biclustering". 2018.
    10.1145/3235830.3235836
  15. VÉSTIAS, MÁRIO; Rui P. Duarte. "Rapid Prototyping of Approximate Signal Processing Using Stochastic Processors on FPGAs". Paper presented in DASIP, 2018.
    Published
  16. Rui Policarpo Duarte. "Top-Down Learning of Embedded Systems Design on FPGA". Paper presented in XII Workshop on Reconfigurable Systems (REC 2017), Aveiro, 2017.
  17. Vestias, M.; Duarte, R.P.; De Sousa, J.T.; Neto, H.; Rui Policarpo Duarte. "Parallel dot-products for deep learning on FPGA". Paper presented in XIV Workshop on Reconfigurable Systems (REC 2018), Caparica, 2017.
    10.23919/FPL.2017.8056863
  18. Vavouras, M.; Duarte, R.P.; Armato, A.; Bouganis, C.-S.. "A hybrid ASIC/FPGA fault-tolerant artificial pancreas". 2017.
    10.1109/SAMOS.2016.7818356
  19. VÉSTIAS, MÁRIO; Rui P. Duarte; Horácio C. Neto. "On the Computation of Approximation Coefficients in ROM-based Redundancy for SEU Mitigation on FPGAs". Paper presented in Workshop on Reliable Field Programmable Logic, 2017.
  20. Rui Policarpo Duarte. "Intelligent Sensors for Real-Time Hazard Detection and Visual Indication on Highways". Paper presented in Conference on Electronics, Telecommunications and Computers (CETC 2016), Lisbon, 2016.
  21. Duarte, Rui Policarpo; Neto, Horácio; Véstias, Mário; Duarte, R.P.; Neto, H.; Véstias, M.; Neto, Horacio; Vestias, Mario; IEEE. "XtokaxtikoX: a stochastic computing-based autonomous cyber-physical system". Paper presented in IEEE International Conference on Rebooting Computing (ICRC 2018), San Diego, 2016.
    10.1109/ICRC.2016.7738716
  22. Duarte, R.P.; Véstias, M.; Neto, H.. "Enhancing stochastic computations via process variation". 2015.
    10.1109/FPL.2015.7293962
  23. VÉSTIAS, MÁRIO; Rui P. Duarte; Horácio C. Neto. "Designing Hardware/Software Systems for Embedded High-Performance Computing". Paper presented in FPGAs for Software Programmers, 2015.
    Published
  24. Duarte, R.P.; Bouganis, C.-S.. "Over-clocking of linear projection designs through device specific optimisations". 2014.
    10.1109/IPDPSW.2014.25
  25. Duarte, R.P.; Bouganis, C.-S.. "High-level linear projection circuit design optimization framework for FPGAs under over-clocking". 2012.
    10.1109/FPL.2012.6339162
  26. Duarte, R.; Neto, H.; Véstias, M.. "Double-precision Gauss-Jordan algorithm with partial pivoting on FPGAs". 2009.
    10.1109/DSD.2009.199
  27. Duarte, R.; Fernandes, J.R.. "A behavioural model for sigma delta fractional PLL". 2009.
  28. Duarte, R.; Fernandes, J.R.. "A comparative study on transformer and inductor based LC tanks for VCOs". 2009.
  29. Rui Policarpo Duarte. "Transport protocols for large bandwidth-delay Product networks - TCP Extensions and Alternative Transport Protocols". 2008.
Edited book
  1. Rui Policarpo Duarte. Introdução aos Sistemas Embebidos com Arduíno (Introduction to Embedded Systems with Arduino). Lisbon, Portugal: FCA. 2020.
    Accepted
Journal article
  1. Jacinto, Gustavo; Policarpo Duarte, Rui. "ZX Fusion: A ZX Spectrum Implementation on an FPGA with Modern Peripherals". Electronics 13 2 (2024): 450. http://dx.doi.org/10.3390/electronics13020450.
    10.3390/electronics13020450
  2. Mário Véstias; Rui P. Duarte; José T. de Sousa; Horácio Neto. "Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units". ACM Transactions on Reconfigurable Technology and Systems (2023): https://doi.org/10.1145/3546182.
    10.1145/3546182
  3. Maria Inês Frutuoso; Horácio C. Neto; Mário P. Véstias; Rui Policarpo Duarte. "Energy-Efficient and Real-Time Wearable for Wellbeing-Monitoring IoT System Based on SoC-FPGA". Algorithms (2023): https://doi.org/10.3390/a16030141.
    10.3390/a16030141
  4. Helena Cruz; Mário Véstias; José Monteiro; Horácio Neto; Rui Policarpo Duarte. "A Review of Synthetic-Aperture Radar Image Formation Algorithms and Implementations: A Computational Perspective". Remote Sensing 14 5 (2022): 1258-1258. https://doi.org/10.3390/rs14051258.
    10.3390/rs14051258
  5. David Mota; Helena Cruz; Pedro R. Miranda; Rui Policarpo Duarte; Jose T. de Sousa; Horacio C. Neto; Mario P. Vestias. "Onboard Processing of Synthetic Aperture Radar Backprojection Algorithm in FPGA". IEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensing 15 (2022): 3600-3611. https://doi.org/10.1109/JSTARS.2022.3169828.
    10.1109/JSTARS.2022.3169828
  6. João D. Lopes; Mário P. Véstias; Rui Policarpo Duarte ; Horácio C. Neto; José T. de Sousa ; D. Lopes, João; Véstias, Mário; et al. "Coarse-Grained Reconfigurable Computing with the Versat Architecture". Electronics 10 6 (2021): 669-669. https://doi.org/10.3390/electronics10060669.
    10.3390/electronics10060669
  7. Daniel Pestana; Pedro R. Miranda; Joao D. Lopes; Rui P. Duarte; Mario P. Vestias; Horacio C. Neto; Jose T. De Sousa. "A Full Featured Configurable Accelerator for Object Detection With YOLO". IEEE Access 9 (2021): 75864-75877. https://doi.org/10.1109/ACCESS.2021.3081818.
    10.1109/ACCESS.2021.3081818
  8. Miranda, Pedro R.; Pestana, Daniel; D. Lopes, João; Duarte, Rui Policarpo; Véstias, Mário; Neto, Horácio C; De Sousa, Jose; et al. "Configurable hardware core for IoT object detection". Future Internet 13 11 (2021): 280-280. http://hdl.handle.net/10400.21/13952.
    10.3390/fi13110280
  9. Mário P. Véstias; Rui Policarpo Duarte; José T. de Sousa; Horácio C. Neto; Véstias, M.P.; Duarte, R.P.; de Sousa, J.T.; et al. "Moving Deep Learning to the Edge". Algorithms 13 5 (2020): 125-125. https://doi.org/10.3390/a13050125.
    10.3390/a13050125
  10. Mario P. Vestias; Rui P. Duarte; Jose T. De Sousa; Horacio C. Neto. "A Configurable Architecture for Running Hybrid Convolutional Neural Networks in Low-Density FPGAs". IEEE Access 8 (2020): 107229-107243. https://doi.org/10.1109/ACCESS.2020.3000444.
    10.1109/ACCESS.2020.3000444
  11. Cruz, H.; Duarte, R.P.; Neto, H.; Rui Policarpo Duarte; Cruz, Helena; Duarte, Rui Policarpo; Neto, Horacio. "Embedded fault-tolerant accelerator architecture for synthetic-aperture radar backprojection". Journal of Aerospace Information Systems 16 11 (2020): 512-520. http://www.scopus.com/inward/record.url?eid=2-s2.0-85092374738&partnerID=MN8TOARS.
    Published • 10.2514/1.I010764
  12. Véstias, M.P.; Duarte, R.P.; de Sousa, J.T.; Neto, H.C.. "A fast and scalable architecture to run convolutional neural networks in low density FPGAs". Microprocessors and Microsystems 77 (2020): http://www.scopus.com/inward/record.url?eid=2-s2.0-85085234927&partnerID=MN8TOARS.
    10.1016/j.micpro.2020.103136
  13. Joao Vieira; Rui P. Duarte; Horacio C. Neto. "kNN-STUFF: kNN STreaming Unit for Fpgas". IEEE Access 7 (2019): 170864-170877. https://doi.org/10.1109/ACCESS.2019.2955864.
    10.1109/ACCESS.2019.2955864
  14. Véstias, Mário; Duarte, Rui Policarpo; De Sousa, Jose; Cláudio de Campos Neto, Horácio; Véstias, M.P.; Duarte, R.P.; de Sousa, J.T.; Neto, H.C.. "Fast convolutional neural networks in low density FPGAs using zero-skipping and weight pruning". Electronics (Switzerland) 8 11 (2019): http://hdl.handle.net/10400.21/10735.
    10.3390/electronics8111321
  15. Duarte, R.P.; Bouganis, C.-S.. "ARC 2014 over-clocking KLT designs on FPGAs under process, voltage, and temperature variation". ACM Transactions on Reconfigurable Technology and Systems 9 1 (2015): http://www.scopus.com/inward/record.url?eid=2-s2.0-84954324092&partnerID=MN8TOARS.
    10.1145/2818380
Newspaper article
  1. Rui Policarpo Duarte. "Os 50 Anos do Primeiro Processador/The 50 Years of the First Processor", Expresso, 2021, https://expresso.pt/opiniao/2021-05-31-Os-50-anos-do-primeiro-processador-ce86bb60.
Online resource
  1. Rui Policarpo Duarte. Coursera Global Translation Community (Portuguese translation) of the courses: ``Introduction to FPGA Design for Embedded Systems,'' ``Architecting Smart IoT Devices,'' ``Computer Architecture.''. 2017.
Preprint
  1. Cruz, Helena; Flores, Paulo; Véstias, Mário; Monteiro, José; Neto, Horácio; Duarte, Rui Policarpo. Corresponding author: Cruz, Helena. "Algorithm-Specific Optimizations for On-Board Real-Time Backprojection on FPGA". 2023. http://dx.doi.org/10.20944/preprints202312.0640.v1.
    10.20944/preprints202312.0640.v1
  2. Gustavo Jacinto; Rui Policarpo Duarte. "ZX Fusion: A ZX Spectrum Implementation on an FPGA With Modern Peripherals". 2023. https://doi.org/10.20944/preprints202311.0956.v1.
    10.20944/preprints202311.0956.v1
Report
  1. Rui Policarpo Duarte. 2020. D1: deliverable #1 for project SARRROCA.
  2. Rui Policarpo Duarte. 2014. Deliverable D3.2 for project BAMBI - Emulation of Hardware Building Blocks.
  3. Rui Policarpo Duarte. 2014. Deliverable D3.4 for project DeSyRe - Final Implementation of the DeSyRe online testing, graceful degradation, and Virtualization support.
Thesis / Dissertation
  1. Rui Policarpo Duarte. "Variation-aware high-level DSP circuit design optimisation framework for FPGAs". PhD, Imperial College London, 2014. https://spiral.imperial.ac.uk/handle/10044/1/24657.
    https://doi.org/10.25560/24657
Website
  1. Rui Policarpo Duarte. Afia lápis. 2019. https://www.afia-lapis.org.
  2. Rui Policarpo Duarte. Jornadas Sobre Sistemas Reconfiguráveis / Workshop on Reconfigurable Systems. 2019. https://sites.google.com/view/sistemas-reconfiguraveis/.
  3. Rui Policarpo Duarte. Project SARRROCA. 2018. https://web.tecnico.ulisboa.pt/ist14551/projs/sarrroca/.
Working paper
  1. Rui Policarpo Duarte. 2017. "Making data center computations fast, but not so furious". https://arxiv.org/pdf/1704.05112.

Intellectual property

Patent
  1. Rui Policarpo Duarte. 2007. "Modular signalling system to detect vehicles on a highway". Portugal.
    Expired

Other

Other output
  1. Stochastic theater: stochastic datapath generation framework for fault-tolerant IoT sensors. Stochastic Computing has emerged as a competitive computing paradigm that produces fast and simple implementations of arithmetic operations, while offering high levels of parallelism, and graceful degradation of the results when in the presence of errors. IoT devices are often operate under limited power and area constraints and subjected to harsh environments, for which, traditional computing par. 2018. Duarte, Rui Policarpo; Véstias, Mário; Carvalho, Carlos; Casaleiro, João; Rui Policarpo Duarte; Fundação para a Ciência e Tecnologia. http://hdl.handle.net/10400.21/9244.
    DUARTE, Rui Policarpo; [et al] – Stochastic theater: stochastic datapath generation framework for fault-tolerant IoT sensors. i-ETC: ISEL Academic Journal of Electronics, Telecommunications and Computers. ISSN 2182-4010. Vol. 4, N.º 1 (2018), pp. 1-9
  2. On the Feasibility of GPON Fiber Light Energy Harvesting for the Internet of Things. The emerging concept of smart cities demands for a large number of electronic devices, like sensors and actuators, distributed over several public spaces and buildings. The Internet of Things (IoT) has a key role in connecting devices to the Internet. However, the significant number of devices makes the maintenance task of the entire network difficult and expensive. To mitigate this problem, consi. 2018. Casaleiro, João Carlos; Carvalho, Carlos Ferreira; Fazenda, Pedro Viçoso; Duarte, Rui Policarpo; Rui Policarpo Duarte. http://journals.isel.pt/index.php/i-ETC/article/view/56.
    10.34629/ipl.isel.i-ETC.56
Activities

Oral presentation

Presentation title Event name
Host (Event location)
2018 Stochastic processors on FPGAs to compute sensor data towards fault-tolerant IoT systems 2018 IEEE Conference on Dependable and Secure Computing (DSC 2018)
(Kaohsiung, Taiwan)
2016/07 Introduction to Stochastic Computing
INESC-ID (Lisbon, Portugal)
2014 Simulation of Bayesian Machines with Modelsim
Instituto de Sistemas e Robótica (Coimbra, Portugal)

Supervision

Thesis Title
Role 		Degree Subject (Type)
Institution / Organization
2020/02 - Current (Wearable) IoT System for People and Environment Monitoring
Supervisor
 Electronics and Computer Engineering (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2020/02 - Current Improved GNSS/GPS receiver on FPGA
Supervisor
 Computer Science and Engineering (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2020/02 - Current Accelerator for real-time on-board processor of satellite images
Supervisor
 Electronics and Computer Engineering (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2020/01 - Current Digital System Design Optimization and Fault-Tolerance for Airborne SAR Systems
Supervisor of Helena Cruz
 Computer Science and Engineering (PhD)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2019/09 - Current SoC-FPGA accelerated BDD-based model checking
Supervisor of Rúben Teixeira
 Computer Science and Engineering (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2018/03 - Current Complementary environment, passenger and vehicle monitoring for improved Advanced Driver-Assistance Systems (ADAS)
Supervisor
 Computer Science and Engineering (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2018/03 - Current Fault-tolerant digital controller for solar power regulator for sattelites/space expeditions on FPGAs
Supervisor
 Aeronautics (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2017/03 - Current An FPGA HW/SW architecture for temporal pattern extraction in genetic expression using bi-clustering
Supervisor of Cristiano Rebelo
 Electronics and Computer Engineering (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2017/03 - Current An OpenCL accelerator for temporal pattern extraction in genetic expression using bi-clustering
Supervisor of Álvaro Simões
 Computer Science and Engineering (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2021 - 2021 ECSS-E-ST-50-15C Compliant CAN for Space Systems - Open-Source HW and SW Framework for Microcontrollers and Systems-On-a-Chip
Supervisor
 Engenharia Informática e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2017/09 - 2019/11 Multi-Core Fault Tolerance Mechanism for Airborne SAR Systems
Supervisor
 Computer Science and Engineering (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2017/09 - 2019/06 FPGA-Based Traffic-Sign Detection and Classification
Supervisor
 Electronics and Computer Engineering (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2017/03 - 2019/06 Vehicle classification system with neural networks on FPGA
Supervisor of Guilherme Lima
Universidade de Lisboa Instituto Superior Técnico, Portugal
2018/03 - 2019/05 Educational Reconfigurable System for Teaching Computer Architectures based on the P4 Processor
Supervisor of Dinis Madeira
 Computer Science and Engineering (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2019 - 2019 FPGA-Based Traffic-Sign Classification
Co-supervisor
 Engenharia Electrotécnica e de Computadores (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2014/09 - 2015/10 Probabilistic Accelerator for the NIOS soft-processor
Co-supervisor
 Electrical and computer engineering (Master)
Universidade de Coimbra Departamento de Engenharia Electrotécnica e de Computadores, Portugal

Event organisation

Event name
Type of event (Role) 		Institution / Organization
2020 - 2021 Design Competition 2021 organization - In this competition each has an autonomous player connected to a referee. Tasks involved preparing all the files for the competition, along with a website, promotion of the event, request prize donations and moderated the session during the XVII Workshop of Reconfigurable System (XVII Jornadas sobre sistemas reconfiguraveis) as a way to attract students to reconfigurable computing. (2020 - 2021/02)
Workshop (President of the Organising Committee)
 Universidade do Porto Faculdade de Engenharia, Portugal
2020/02/10 - 2020/02/11 XVI Jornadas sobre Sistemas Reconfiguráveis / Workshop on reconfigurable systems (2020/02/10 - 2020/02/11)
Conference (President of the Organising Committee)
 Universidade de Lisboa Instituto Superior Técnico, Portugal
2019/11/01 - 2020/02 BlokusDuo Design Competition 2020 organization - In this competition each has an autonomous player connected to a referee. Tasks involved preparing all the files for the competition, along with a website, promotion of the event, request prize donations and moderated the session during the XVI Workshop of Reconfigurable System (XVI Jornadas sobre sistemas reconfiguraveis) as a way to attract students to reconfigurable computing. http://web.tecnico.ulisboa.pt/rui.duarte/BlokusDuo2020/ (2020/02/10 - 2020/02/10)
Workshop (President of the Organising Committee)
 Universidade de Lisboa Instituto Superior Técnico, Portugal

Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
2019/02/14 - 2019/02/15 XV Jornadas sobre sistemas reconfiguráveis / XV Workshop on Reconfigurable Systems (2019/02/14 - 2019/02/15)
Conference (Member of the Organising Committee)
 Universidade do Minho - Campus de Azurém, Portugal
2018/10/05 - 2019/02/14 BlokusDuo Design Competition 2019 organization - In this competition each has an autonomous player connected to a referee. Tasks involved preparing all the files for the competition, along with a website, promotion of the event, request prize donations and moderated the session during the XV Workshop of Reconfigurable System (XV Jornadas sobre sistemas reconfiguraveis) as a way to attract students to reconfigurable computing. http://web.tecnico.ulisboa.pt/rui.duarte/BlokusDuo2019/ (2019/02/14 - 2019/02/14)
Workshop (President of the Organising Committee)
 Universidade do Minho - Campus de Azurém, Portugal

Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
2017/09/14 - 2018/02/15 BlokusDuo Design Competition 2018 organization - In this competition each has an autonomous player connected to a referee. Tasks involved preparing all the files for the competition, along with a website, promotion of the event, request prize donations and moderated the session during the XIV Workshop of Reconfigurable System (XIV Jornadas sobre sistemas reconfiguraveis) as a way to attract students to reconfigurable computing. http://web.tecnico.ulisboa.pt/rui.duarte/BlokusDuo2018/ (2018/02/15 - 2018/02/15)
Workshop (President of the Organising Committee)
 Universidade Nova de Lisboa Faculdade de Ciências e Tecnologia, Portugal

Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal

Jury of academic degree

Topic
Role 		Candidate name (Type of degree)
Institution / Organization
2019/09 Sistema de Reconhecimento de Imagens com Redes Neuronais Convolucionais (BSc project)
(Thesis) Main arguer
 António Joaquim Martins Henriques (Other)
Instituto Politécnico de Lisboa Instituto Superior de Engenharia de Lisboa, Portugal
2019/02 A Massively Parallel processor using the RISC-V instruction set (MSc project)
(Thesis) Main arguer
 João Filipe Monteiro Rodrigues (Other)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2019 Educational Reconfigurable System for Teaching Computer Architectures based on the P4 Processor
Supervisor
 Dinis Madeira (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2018/12 Otimização de Redes Neuronais Convolucionais em FPGA utilizando Técnicas de Compressão
(Thesis) Main arguer
 Tiago Alexandre Mateus Peres (Master)
Instituto Politécnico de Lisboa Instituto Superior de Engenharia de Lisboa, Portugal
2018/10 Optimized memory sub-system for the Scratch soft-GPGPU
(Thesis) Main arguer
 João Miguel Morgado Pereira Vieira (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2018/06 IoT for the Smart Home
(Thesis) Main arguer
 António Gonçalves Vian Costa (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2018/06 Character recognition using Convolutional Neural Networks (BSc project)
(Thesis) Main arguer
 Ricardo Sampaio (Other)
Instituto Politécnico de Lisboa Instituto Superior de Engenharia de Lisboa, Portugal
2018/02 Optimized memory sub-system for the Scratch soft-GPGPU (MSc project)
(Thesis) Main arguer
 João Miguel Morgado Pereira Vieira (Other)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2018/01 An industrial IoT application using the Zynq Soc FPGA
(Thesis) Main arguer
 João Filipe Mota (Other)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2018/01 Parallelization of Conditional Path Detection in Graphs
(Thesis) Main arguer
 Rafael Santos (Other)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2018 Multi-Core Fault Tolerance Mechanism for Airborne SAR Systems
Supervisor
 Helena Cruz (Master)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2017/06 Layer 3 MPLS VPNs
(Thesis) Main arguer
 Hamid Khanpour (Master)
Instituto Politécnico de Lisboa Área Departamental de Engenharia de Electrónica e Telecomunicações e de Computadores, Portugal
2017/01 Breaking the security of crypto systems using cache side-channel attacks (MSc project)
(Thesis) Main arguer
 Ricardo Miguel da Silva Santos (Other)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2016/09 Methodology to Accelerate Diagnostic Coverage Assessment: M-AC/DC
(Thesis) Arguer
 Frederico Ferlini (PhD)
Universidade Federal de Santa Catarina, Brazil
2016/09 Dedicated hardware system for AES encryption on an FPGA
(Thesis) Main arguer
 Bruno Silva and Rui Lincho (Other)
Instituto Politécnico de Lisboa Instituto Superior de Engenharia de Lisboa, Portugal
2016/09 Lab activities with Cisco Packet Tracer (BSc project)
(Thesis) Main arguer
 Filipe Luz and José Apolinário (Other)
Instituto Politécnico de Lisboa Instituto Superior de Engenharia de Lisboa, Portugal

Association member

Society Organization name Role
2016 - Current ACM - Association for Computing Machinery Member
2015 - Current IEEE - Institute of Electrical and Electronics Engineers, Circuits and Systems Society member
2006 - Current OE - Ordem dos Engenheiros / Portuguese Professional Engineering Society
2004 - 2006 Audio Engineering Society student member

Committee member

Activity description
Role 		Institution / Organization
2016 - 2019 Member of the department committee for the Department of Computer Science and Engineering at Instituto Superior Técnico, University of Lisbon
Member
 Universidade de Lisboa Instituto Superior Técnico, Portugal
2014 - 2016 Member of the scientific committee of the Department of Sciences and Technologies at the Autonomous University of Lisbon
Member
 Universidade Autónoma de Lisboa Departamento de Ciências e Tecnologias, Portugal
2015 - 2015 Member of the group that worked with the Portuguese accreditation authority for higher education (CAE), for the approval of a new degree in Electronics and Telecommunications Engineering at the Autonomous University of Lisbon. The degree has been offered since 2016.
Advisor / Consultant
 Universidade Autónoma de Lisboa Departamento de Ciências e Tecnologias, Portugal
2015 - 2015 Responsible for elaborating the laboratory experiments and requirements for all courseworks, and the equipment procurement for the new degree in Electronics and Telecommunications Engineering proposal, at the Autonomous University of Lisbon
Coordinator
 Universidade Autónoma de Lisboa Departamento de Ciências e Tecnologias, Portugal

Conference scientific committee

Conference name Conference host
2020/02 - 2020/02 REC2020 - XVI Workshop on Reconfigurable Systems Instituto Superior Técnico, University of Lisbon
2019/02/22 - 2019/02/23 IEEE 6th Portuguese Meeting on Bioengineering Instituto Superior de Engenharia de Lisboa
2019 - 2019 REC2019 - XV Workshop on Reconfigurable Systems Universidade do Minho, Guimarães
2018/12/10 - 2018/12/13 DSC2018 - IEEE Conference on Dependable and Secure Computing National Sun Yat-sen University, Kaohsiung, Taiwan
2018 - 2018 REC2018 - XIV Workshop on Reconfigurable Systems Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa
2017/11/08 - 2017/11/09 ICRC2017 - 2nd IEEE International Conference on Rebooting Computing IEEE Rebooting Computing
2017/08/07 - 2017/08/10 DSC2017 - IEEE Conference on Dependable and Secure Computing National Chiao Tung University, Taipei, Taiwan
2016/12/06 - 2016/12/07 CETC2016 - 3rd Conference on Electronics, Telecommunications and Computers Instituto Superior de Engenharia de Lisboa

Consulting

Activity description Institution / Organization
2018 - 2018 Adviser on hardware and firmware for wireless ultra-low-power autonomous/wearable embedded systems for acquisition and analysis of EEG signals using a headband for e-gamers. Acted as Chief Hardware Officer of Emotai in Brinc (startup accelerator) headquarters in Hong Kong. Emotai, Hong Kong SAR China

Course / Discipline taught

Academic session Degree Subject (Type) Institution / Organization
2018 - 2019 Introduction to Computer Architectures, 1st semester 2018/2019, https://fenix.tecnico.ulisboa.pt/disciplinas/IAC4517957/2018-2019/1-semestre computer science and engineering (Licenciatura) Universidade de Lisboa Instituto Superior Técnico, Portugal
2018 - 2019 Computer Organization, 1st semester 2018/2019, https://fenix.tecnico.ulisboa.pt/disciplinas/OC1117957/2018-2019/1-semestre Computer Science and Engineering (Mestrado integrado) Universidade de Lisboa Instituto Superior Técnico, Portugal
2018 - 2019 Computer Organization, 1st semester 2018/2019; https://fenix.tecnico.ulisboa.pt/disciplinas/OC1217957/2018-2019/1-semestre Computer Science and Engineering (Mestrado integrado) Universidade de Lisboa Instituto Superior Técnico Campus Taguspark, Portugal
2017 - 2018 Distributed Systems, 2nd semester 2017/2018, https://fenix.tecnico.ulisboa.pt/disciplinas/SDis12645111326/2017-2018/2-semestre Computer Science and Engineering (Licenciatura) Universidade de Lisboa Instituto Superior Técnico, Portugal
2017 - 2018 Distributed Systems, 2nd semester 2017/2018, https://fenix.tecnico.ulisboa.pt/disciplinas/SDis15111326/2017-2018/2-semestre Computer Science and Engineering (Licenciatura) Universidade de Lisboa Instituto Superior Técnico, Portugal
2017 - 2018 Introduction to Computer Architectures, 1st semester 2017/2018, https://fenix.tecnico.ulisboa.pt/disciplinas/IAC451795/2017-2018/1-semestre Computer Science and Engineering (Licenciatura) Universidade de Lisboa Instituto Superior Técnico, Portugal
2017 - 2018 Computer Organization, 1st semester 2017/2018, https://fenix.tecnico.ulisboa.pt/disciplinas/OC111795/2017-2018/1-semestre Computer Science and Engineering (Licenciatura) Universidade de Lisboa Instituto Superior Técnico, Portugal
2017 - 2018 Computer Organization, 1st semester 2017/2018, https://fenix.tecnico.ulisboa.pt/disciplinas/OC121795/2017-2018/1-semestre Computer Science and Engineering (Licenciatura) Universidade de Lisboa Instituto Superior Técnico Campus Taguspark, Portugal
2016 - 2017 Introduction to Computer Architectures, 1st semester 2016/2017, https://fenix.tecnico.ulisboa.pt/disciplinas/IAC45179/2016-2017/1-semestre Computer Science and Engineering (Licenciatura) Universidade de Lisboa Instituto Superior Técnico, Portugal
2016 - 2017 Introduction to Computer Architecture, 1st semester 2016/2017, https://fenix.tecnico.ulisboa.pt/disciplinas/IAC3179/2016-2017/1-semestre Computer Science and Engineering (Licenciatura) Universidade de Lisboa Instituto Superior Técnico Campus Taguspark, Portugal
2016 - 2017 Computer Organization, 1st semester 2016/2017, https://fenix.tecnico.ulisboa.pt/disciplinas/OC11179/2016-2017/1-semestre Computer Science and Engineering (Licenciatura) Universidade de Lisboa Instituto Superior Técnico, Portugal
2016 - 2017 Computer Organization, 1st semester 2016/2017, https://fenix.tecnico.ulisboa.pt/disciplinas/OC12179/2016-2017/1-semestre Computer Science and Engineering (Licenciatura) Universidade de Lisboa Instituto Superior Técnico Campus Taguspark, Portugal
2016 - 2017 Operating Systems, 1st semester 2016/2017, https://fenix.tecnico.ulisboa.pt/disciplinas/SO45179/2016-2017/1-semestre Computer Science and Engineering (Licenciatura) Universidade de Lisboa Instituto Superior Técnico, Portugal
2016 - 2017 Operating Systems, 1st semester 2016/2017, https://fenix.tecnico.ulisboa.pt/disciplinas/SO7179/2016-2017/1-semestre Computer Science and Engineering + Telecommunications and Informatics Engineering (Licenciatura) Universidade de Lisboa Instituto Superior Técnico Campus Taguspark, Portugal
2016 - 2017 Distributed Systems, 2nd semester, https://fenix.tecnico.ulisboa.pt/disciplinas/SDis12645111326/2016-2017/2-semestre Computer Science and Engineering (Licenciatura) Universidade de Lisboa Instituto Superior Técnico, Portugal
2016 - 2017 Distributed Systems, 2nd semester, 2016/2017, https://fenix.tecnico.ulisboa.pt/disciplinas/SDis15111326/2016-2017/2-semestre Computer Science and Engineering (Licenciatura) Universidade de Lisboa Instituto Superior Técnico Campus Taguspark, Portugal
2015 - 2016 Computer Networking, 2nd semester computer science (Licenciatura) Instituto Politécnico de Lisboa Instituto Superior de Engenharia de Lisboa, Portugal
2015 - 2016 Circuit Analysis, 1st semester, Electronics and Telecommunications (Licenciatura) Universidade Autónoma de Lisboa Departamento de Ciências e Tecnologias, Portugal
2015 - 2016 Electronics I, 2nd semester Electronics and Telecommunications engineering (Licenciatura) Universidade Autónoma de Lisboa Departamento de Ciências e Tecnologias, Portugal
2015 - 2016 Object-Oriented Programming, 1st semester Computer Engineering (Licenciatura) Universidade Autónoma de Lisboa Departamento de Ciências e Tecnologias, Portugal
2015 - 2016 Computer Architectures, 2nd semester Computer Engineering (Licenciatura) Universidade Autónoma de Lisboa Departamento de Ciências e Tecnologias, Portugal
2015 - 2016 Programming Paradigms, 2nd semester Programming Paradigms (Licenciatura) Universidade Autónoma de Lisboa Departamento de Ciências e Tecnologias, Portugal
2014 - 2015 Computer Architectures, 2nd semester computer science (Licenciatura) Universidade Autónoma de Lisboa Departamento de Ciências e Tecnologias, Portugal
2012 - 2012 Introduction to Matlab and Python, 3rd term, Electrical and Electronic Engineering (Master) Imperial College London Department of Electrical and Electronic Engineering, United Kingdom
2012 - 2012 Digital System Design, 2nd term Electrical and Electronic Engineering (Master) Imperial College London Department of Electrical and Electronic Engineering, United Kingdom
2012 - 2012 High-Level Synthesis Project, 3rd term Electrical and Electronic Engineering (Master) Imperial College London Department of Electrical and Electronic Engineering, United Kingdom
2011 - 2011 Introduction to Matlab and Python, 3rd term Electrical and Electronic Engineering (Master) Imperial College London Department of Electrical and Electronic Engineering, United Kingdom
2011 - 2011 Digital System Design, 2nd term Electrical and Electronic Engineering (Master) Imperial College London Department of Electrical and Electronic Engineering, United Kingdom
2011 - 2011 High-Level Synthesis Project, 3rd term Electrical and Electronic Engineering (Master) Imperial College London Department of Electrical and Electronic Engineering, United Kingdom
2010 - 2010 Digital System Design, 2nd term Electrical and Electronic Engineering (Master) Imperial College London Department of Electrical and Electronic Engineering, United Kingdom
2010 - 2010 High-Level Synthesis Project, 3rd term Electrical and Electronic Engineering (Master) Imperial College London Department of Electrical and Electronic Engineering, United Kingdom
2008 - 2009 Mechanisms for Quality of Service Support in the Internet, 1st semester 2008/2009, https://fenix.tecnico.ulisboa.pt/disciplinas/MSQSI-2/2008-2009/1-semestre Integrated Master in Electrical and Computer Engineering (Mestrado integrado) Universidade de Lisboa Instituto Superior Técnico, Portugal
2008 - 2009 Mechanisms for Quality of Service Support in the Internet, 1st semester, https://fenix.tecnico.ulisboa.pt/disciplinas/MSQSI2/2008-2009/1-semestre Master Degree in Communication Networks Engineering (Mestrado) Universidade de Lisboa Instituto Superior Técnico Campus Taguspark, Portugal
2008 - 2009 Computer Networks, 2nd semester Computer Engineering (Licenciatura) Universidade Autónoma de Lisboa Departamento de Ciências e Tecnologias, Portugal
2007 - 2008 Computer Networks, 2nd semester, https://fenix.tecnico.ulisboa.pt/disciplinas/RC/2007-2008/2-semestre Communication Networks Engineering; Electronics Engineering (Licenciatura) Universidade de Lisboa Instituto Superior Técnico, Portugal
2007 - 2008 Mechanisms for Quality of Service Support in the Internet, 1st semester, https://fenix.tecnico.ulisboa.pt/disciplinas/MSQSI/2007-2008/1-semestre Communication Networks Engineering (Mestrado) Universidade de Lisboa Instituto Superior Técnico Campus Taguspark, Portugal
2007 - 2008 Mechanisms for Quality of Service Support in the Internet Integrated Master in Electrical and Computer Engineering (Mestrado integrado) Universidade de Lisboa Instituto Superior Técnico, Portugal
2006 - 2007 Basic Communication Networks, 2nd semester, https://fenix.tecnico.ulisboa.pt/disciplinas/IRT/2006-2007/2-semestre Degree (5 years) in Electrical and Computer Engineering (Licenciatura) Universidade de Lisboa Instituto Superior Técnico, Portugal
2006 - 2007 Basic Communication Networks, 1st semester, https://fenix.tecnico.ulisboa.pt/disciplinas/AU8/2006-2007/1-semestre Information and Communication Networks Engineering Universidade de Lisboa Instituto Superior Técnico Campus Taguspark, Portugal
2006 - 2007 Computer Networks I Electronics Engineering (Licenciatura) Universidade de Lisboa Instituto Superior Técnico Campus Taguspark, Portugal
2005 - 2006 Computer Networks II, 2nd semester, https://fenix.tecnico.ulisboa.pt/disciplinas/RCII/2005-2006/2-semestre Information and Communication Networks Engineering Universidade de Lisboa Instituto Superior Técnico Campus Taguspark, Portugal
2005 - 2006 Basic Communication Networks, 1st semester, https://fenix.tecnico.ulisboa.pt/disciplinas/RCI/2005-2006/1-semestre Information and Communication Networks Engineering (Licenciatura) Universidade de Lisboa Instituto Superior Técnico Campus Taguspark, Portugal
2005 - 2006 Computer Networks I Electronics Engineering (Licenciatura) Universidade de Lisboa Instituto Superior Técnico Campus Taguspark, Portugal

Journal scientific committee

Journal title (ISSN) Publisher
2020/04 - Current Electronics (Switzerland) - Guest Editor of Special Issue of Fault-Tolerant Architectures and Applications (20799292) MDPI
2018 - 2018 VLSI Design, Manuscript ID: 6498031 Hindawi
2018 - 2018 IEEE Access, Manuscript IDs: Access-2018-06929, Access-2018-17796, Access-2018-21638 (2169-3536) Institute of Electrical and Electronics Engineers
2018 - 2018 IEEE Embedded Systems Letters (1943-0671) Institute of Electrical and Electronics Engineers
2018 - 2018 ISEL Academic Journal of Electronics Telecommunications and Computers ( 2182-4010) Instituto Superior de Engenharia de Lisboa (ISEL)
2018 - 2018 International Journal of Reconfigurable Computing, Manuscript ID 1403181 (1687-7209) Hindawi Limited
2018 - 2018 IEEE Transactions on Multimedia, Manuscript ID MM-008499 (1941-0077) Institute of Electrical and Electronics Engineers
2017 - 2017 IEEE Access, Manuscript ID Access-2017-0813, Access-2017-01851 (2169-3536) Institute of Electrical and Electronics Engineers
2017 - 2017 IEEE Transactions on Industrial Electronics, Manuscript No. 17-TIE-1824 (1557-9948) Institute of Electrical and Electronics Engineers
2017 - 2017 ISEL Academic Journal of Electronics Telecommunications and Computers (2182-4010) Instituto Superior de Engenharia de Lisboa (ISEL)
2016 - 2016 IEEE Transactions on Circuits and Systems for Video Technology, Manuscript TCSVT-00521-2016 (1558-2205) Institute of Electrical and Electronics Engineers
2014 - 2014 IEEE Transactions on Circuits and Systems for Video Technology, Manuscript TCSVT 8671 (1558-2205) Institute of Electrical and Electronics Engineers
2010 - 2010 IET Computers & Digital Techniques (1751-861X) Institution of Electrical Engineers

Legal proceeding

Activity description Case
2020/03/01 - Current Expert appointed by the court (Tribunal Administrativo de Lisboa) on a dispute about a public service acquisition proceedings. 483-19.5BELSB
2019/01/07 - 2019/12/27 Expert appointed by the court (Tribunal Administrativo de Lisboa) on a dispute about a public service acquisition proceedings. proc. Nº 949/17.1BELRA

Mentoring / Tutoring

Topic Student name
2017/11 - 2018/01 Embedded systems Benjamin D'Aletto
2016/06 - 2016/08 Summer Internship Advisor at INESC-ID Guilherme Beja
2016/06 - 2016/08 Summer Internship Advisor at INESC-ID José Dias
2015/12 - 2016/07 Electronics Club at Universidade Autónoma de Lisboa Bruno Martins, Hugo Inocêncio, Marco Carmo, António Almeida, Luis Galhoz
2015/06 - 2015/07 R&D Intern Advisor between Cardio-Id Technologies and IST/ULisbon André Duarte
Distinctions

Award

2020 Diplome of Teaching Excellency: recognition on the pedagogical excellence on teaching Computer Organization on the academic year 2018/2019 at Instituto Superior Técnico (QUC = 9 out of 9)
Universidade de Lisboa Instituto Superior Técnico, Portugal
2019 winner of the IEEE Access 2019 Best Multimedia Award (Part 2) for the article "kNN-STUFF: kNN STreaming Unit for Fpgas."
IEEE, United States
2016 Best paper award, Technological Innovation for Cyber-Physical Systems, Volume 470 of the series IFIP Advances in Information and Communication Technology, with paper "Variation-Aware Optimisation for Reconfigurable Cyber-Physical Systems"; March 2016
Springer Nature, Luxembourg
2011 PhD Grant SFRH/BD/69587
Fundação para a Ciência e a Tecnologia, Portugal
2010 Design-London Fellowship
Imperial College London, United Kingdom

Other distinction

2020 Sponsorship of prizes for BlokusDuo System Design Competition 2020 by Trenz Electronic and Intel Corp
Intel Corp, United States

Trenz Electronic GmbH, Germany
2019 Sponsorship of prizes for BlokusDuo System Design Competition 2019 by Trenz Electronic and Intel Corp
Trenz Electronic GmbH, Germany

Intel Corp, United States
2018 Donation of FPGA boards for updating Introduction to Computer Architectures syllabus at IST/ULisbon by Intel Corp
Intel Corp, United States
2018 Sponsorship of prizes for BlokusDuo System Design Competition 2018 by Trenz Electronic and Intel Corp
Intel Corp, United States

Trenz Electronic GmbH, Germany
2015 Donation of analog electronics kits by Texas Instruments for UAL
Texas Instruments Inc, United States