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José João Henriques Teixeira de Sousa. Completed the Doutoramento in Electronic Engineering in 1998 by Imperial College London. Is Assistant Professor in Universidade de Lisboa Instituto Superior Técnico, Tech startup CEO/CTO in IObundle, LDA and Researcher in Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa. Published 10 articles in journals. Has 8 book(s). Has 4 patent(s) registered. Supervised 1 PhD thesis(es) e co-supervised 1. Has received 3 awards and/or honors. Participates and/or participated as Principal investigator in 3 project(s) and Researcher in 2 project(s). In his curriculum Ciência Vitae the most frequent terms in the context of scientific, technological and artistic-cultural output are: Embedded computing; Deep learning; Convolutional neural network; Field-programmable gate array; Low power architectures; RISC-V; CGRAs; Heterogeneous computing; Bluetooth; demodulators; discriminators; frequency shift keying; low-power electronics; packet radio networks; Bluetooth low energy; Bluetooth-LE; SNR packets rejection; all-digital GFSK demodulator; bit decision unit; current 170 muA; frequency 1 MHz; intermediate-frequency input signal; low-IF Gaussian frequency-shift keying; quadrature FM discriminator; size 130 nm; voltage 1; 2 V; Bit error rate; Demodulation; Frequency shift keying; Receivers; Signal to noise ratio; CMOS; GFSK; demodulator; low-IF; low-power; Electrical and Computer Engineering - Computer Systems (Hardware/Software); .
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Identification

Personal identification

Full name
José João Henriques Teixeira de Sousa

Citation names

  • Sousa, José T. de

Author identifiers

Ciência ID
BE18-E262-E0EC
ORCID iD
0000-0001-7525-7546
Google Scholar ID
ai6ekBAAAAAJ
Scopus Author Id
7102813024
Education
Degree Classification
1998
Concluded
 Electrical Engineering (Doutoramento)
Major in Electronics
Imperial College London, United Kingdom
"Diagnosis of Interconnect Defects in Electronic Assemblies" (THESIS/DISSERTATION)
1992/09/01
Concluded
 Engenharia Electrotécnica e de Computadores (Mestrado)
Universidade de Lisboa Instituto Superior Técnico, Portugal
Affiliation

Science

Category
Host institution 		Employer
1999 - Current Researcher (Research) Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
1998 - 1999 Postdoc (Research) Nokia Bell Labs, United States

Teaching in Higher Education

Category
Host institution 		Employer
1999 - Current Assistant Professor (University Teacher) Universidade de Lisboa Instituto Superior Técnico, Portugal
Universidade de Lisboa Instituto Superior Técnico, Portugal
1999 - Current Assistant Professor (University Teacher) Universidade de Lisboa Instituto Superior Técnico, Portugal
2016 - 2019 Assistant Professor (University Teacher) Universidade de Lisboa, Portugal
2016 - 2019 Assistant Professor (University Teacher) Universidade de Lisboa, Portugal
2016 - 2019 Assistant Professor (University Teacher) Universidade de Lisboa, Portugal
2013 - 2016 Assistant Professor (University Teacher) Universidade de Lisboa Instituto Superior Técnico, Portugal
2013 - 2016 Assistant Professor (University Teacher) Universidade de Lisboa Instituto Superior Técnico, Portugal

Others

Category
Host institution 		Employer
2018 - Current Tech startup CEO/CTO IObundle, LDA, Portugal
2017 - 2019 Tech startup CEO IPBLOQ, LDA, Portugal
2001 - 2013 Tech startup CEO/CTO Coreworks S.A., Portugal
Coreworks S.A., Portugal
2004 - 2006 Principal Engineer DAFCA INC, United States
DAFCA INC, United States
1996/06 - 1996/09 Summer Intern LSI Corp, United States
Projects

Grant

Designation Funders
2023/01/01 - 2025/12/31 Artificial Intelligence for Realtime Distributed Systems at the Edge
101096658
Startup participant
IObundle, LDA, Portugal
 Fundação para a Ciência e a Tecnologia
2018 - 2021 PEPCC: Power Efficiency and Performance for Embedded and HPC Systems with Custom CGRAs
PTDC/EEI-HAC/30848/2017
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia
Ongoing
2010/01/01 - 2012 Rendering FPGAs to Multi-Core Embedded Computing
info:eu-repo/grantAgreement/EC/FP7/248976/EU
 European Commission
Concluded
2002/03/01 - 2005 RECALL - A Reconfigurable Architecture for Logic Emulation/Simulation without Layout Compilation
POSC/41896/PT
Researcher
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia
2001/01/01 - 2004 HIPERSAT - A HIgh PERformance hardware-software SAT solver
info:eu-repo/grantAgreement/FCT/Orçamento de Funcionamento/POSC/34562/PT
Principal investigator
Universidade do Algarve Faculdade de Ciências e Tecnologia

Contract

Designation Funders
2018/10/01 - 2022/09/30 Synthetic Aperture Radar Robust Reconfigurable Optimized Computing Architecture
PTDC/EEI-HAC/31819/2017
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia
Concluded
2018/09/01 - 2022/08/31 Wireless Sensor Network for Environmental Monitoring
PTDC/EEI-EEE/30539/2017
Instituto de Telecomunicações, Portugal

Instituto de Telecomunicações, Portugal

Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
Fundação para a Ciência e a Tecnologia
Ongoing
2019/01/01 - 2019/12/31 Instituto de Engenharia de Sistemas e Computadores, Investigação e Desenvolvimento em Lisboa
UID/CEC/50021/2019
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia
Concluded
2013 - 2013 MULTIWORKS - ARQUITECTURA DE MULTIPROCESSAMENTO PARA ÁUDIO DIGITAL
24781
Researcher
Coreworks S.A., Portugal
 Agência Nacional de Inovação SA
Concluded
2011/01/01 - 2012/12/31 Strategic Project - LA 21 - 2011-2012
PEst-OE/EEI/LA0021/2011
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal
 Fundação para a Ciência e a Tecnologia
Concluded
2009 - 2012 SIDEWORKS - PROCESSADOR RECONFIGURÁVEL, COMPILADOR E APLICAÇÕES
3487
Principal investigator
Coreworks S.A., Portugal
 Agência Nacional de Inovação SA
Concluded
2007 - 2010 COREWORKS / NITEC
COREWORKS
Principal investigator
Coreworks S.A., Portugal
 Agência Nacional de Inovação SA
Concluded
2002/03/01 - 2005/02/28 RECALL - A Reconfigurable Architecture for Logic Emulation/Simulation without Layout Compilation
POSI/CHS/41896/2001
 Fundação para a Ciência e a Tecnologia
Concluded
2001/01/01 - 2004/06/30 HIPERSAT - A HIgh PERformance hardware-software SAT solver
POSI/CHS/34562/2000
 Fundação para a Ciência e a Tecnologia
Concluded
Outputs

Publications

Book
  1. Lopes, J.D.; De Sousa, J.T.. Versat, a minimal coarse-grain reconfigurable array. 2017.
    10.1007/978-3-319-61982-8_17
  2. Sousa, José T. de. Boundary-scan interconnect diagnosis. Springer Science \& Business Media. 2006.
  3. Tavares, C.J.; Bungardean, C.; Matos, G.M.; De Sousa, J.T.. Solving SAT with a context-switching virtual clause pipeline and an FPGA embedded processor. 2004.
  4. Cheung, P.Y.K.; Constantinides, G.A.; Sousa, José T. de. Field Programmable Logic and Application. Springer Berlin Heidelberg. 2003.
    Published • 10.1007/b12007
  5. Bhalla, A.; Lynce, I.; De Sousa, J.T.; Marques-Silva, J.. Heuristic-based backtracking for prepositional satisfiability. 2003.
  6. Parreira, A.; Teixeira, J.P.; Pantelimon, A.; Santos, M.B.; De Sousa, J.T.; Parreira, A; Teixeira, JP; et al. Fault simulation using partially reconfigurable hardware. 2003.
    10.1007/978-3-540-45234-8_81
  7. Cheung, P.Y.K.; Constantinides, G.A.; de Sousa, J.T.. Preface. 2003.
  8. De Sousa, J.T.; Gonçalves, F.M.; Barreiro, N.; Moura, J.. DARP - A digital audio reconfigurable processor. 2002.
Book chapter
  1. Sousa, José T. de. "On Defect Level Estimation and the Clustering Effect". In VLSI: Systems on a Chip. Springer US, 2000.
Conference paper
  1. Fiolhais, Luís; Gonçalves, Fernando; Duarte, Rui P.; Véstias, Mário; Sousa, José T. de. "Low energy heterogeneous computing with multiple RISC-V and CGRA cores". 2019.
    10.1109/ISCAS.2019.8702538
  2. Vestias, M.P.; Duarte, R.P.; De Sousa, J.T.; Neto, H.. "Hybrid dot-product calculation for convolutional neural networks in FPGA". 2019.
    10.1109/FPL.2019.00062
  3. Fiolhais, Luís; Gonçalves, Fernando; Duarte, Rui P.; Véstias, Mário; Sousa, Jose T. De. "Low energy heterogeneous computing with multiple RISC-V and CGRA cores". 2019.
    10.1109/ISCAS.2019.8702538
  4. Sousa, José T. de. "Warpbird: an Untethered System on Chip Using RISC-V Cores and the Rocket Chip Infrastructure". 2018.
    10.5281/ZENODO.3679370
  5. Véstias, Mário; Duarte, Rui; Sousa, José T. de; Neto, Horácio. "Lite-CNN: a high-performance architecture to execute CNNs in low density FPGAs". 2018.
  6. Sousa, José T. de. "Fast Fourier Transform on the Versat CGRA". 2017.
    10.5281/ZENODO.3685577
  7. Sousa, José T. de. "Compiler for the Versat reconfigurable architecture". 2017.
    10.5281/ZENODO.3685537
  8. Lopes, J.D.; De Sousa, J.T.; Neto, H.; Vestias, M.. "K-means clustering on CGRA". 2017.
    10.23919/FPL.2017.8056854
  9. Vestias, M.; Duarte, R.P.; De Sousa, J.T.; Neto, H.. "Parallel dot-products for deep learning on FPGA". 2017.
    10.23919/FPL.2017.8056863
  10. Sousa, José T. de. "Versat, a Runtime Partially Reconfigurable Coarse-Grain Reconfigurable Array using a Programmable Controller". 2016.
    10.5281/ZENODO.3685610
  11. Pereira, M.S.; Vaz, J.C.; Leme, C.A.; De Sousa, J.T.; Freire, J.C.. "An ultra-low power low-IF GFSK demodulator for Bluetooth-LE applications". 2015.
    10.1109/ISCAS.2015.7168861
  12. Zuim, R.; Sousa, J.T.; Coelho, C.N.. "A fast SAT solver strategy based on negated clauses". 2006.
    10.1109/VLSISOC.2006.313213
  13. Zuim, R.; De Sousa, J.T.; Coelho, C.N.. "A fast SAT solver algorithm best suited to reconfigurable hardware". 2006.
  14. Conçolves, V.; De Sousa, J.T.; Conçoives, F.. "A low-cost scalable pipelined reconfigurable architecture for simulation of digital circuits". 2005.
    10.1109/FPL.2005.1515768
  15. Bhalla, A.; Lynce, I.; Sousa, José T. de; Marques-Silva, J.. "Heuristic backtracking algorithms for SAT". 2003.
    10.1109/MTV.2003.1250265
  16. Reis, N.A.; De Sousa, J.T.. "On implementing a configware/software SAT solver". 2002.
    10.1109/FPGA.2002.1106685
  17. De Sousa, J.T.; Da Silva, J.M.; Abramovici, M.. "A Configurable Hardware/Software Approach to SAT Solving". 2001.
  18. De Sousa, J.T.; Agrawal, V.D.. "Reducing the complexity of defect level modeling using the clustering effect". 2000.
    10.1109/DATE.2000.840853
  19. Abramovici, M.; De Sousa, J.T.. "A virtual logic algorithm for solving satisfiability problems using reconfigurable hardware". 1999.
  20. Abramovici, Miron; de Sousa, Jose T.; Saab, Daniel. "Massively-parallel easily-scalable satisfiability solver using reconfigurable hardware". 1999.
  21. M. Abramovici; Sousa, José T. de; D. Saab; Abramovici, M.; de Sousa, J.T.; Saab, D.. "A massively-parallel easily-scalable satisfiability solver using reconfigurable hardware". 1999.
    10.1109/DAC.1999.782036
  22. de Sousa, J.T.; Cheung, P.Y.K.. "Improved diagnosis of realistic interconnect shorts". 1997.
  23. Sousa, José T. de; Shen, T.; Cheung, P.Y.K.. "Realistic fault extraction for boards". 1996.
  24. Sousa, J.T.; Shen, T.; Cheung, P.Y.K.. "On structural diagnosis for interconnects". 1996.
  25. Sousa, J.T.; Goncalves, F.M.; Teixeira, J.P.; Williams, T.W.. "Fault modeling and defect level projections in digital ICs". 1994.
  26. Casimiro, A.P.; Sousa, J.J.T.; Goncalves, F.M.; Teixeira, J.P.. "Test quality improvement by physical testability enhancement". 1992.
    10.1109/CMPEUR.1992.218421
  27. Saraiva, M.; Casimiro, P.; Santos, M.; Sousa, J.T.; Goncalves, F.; Teixeira, I.; Teixeira, J.P.. "Physical DFT for High Coverage of Realistic Faults". 1992.
    10.1109/TEST.1992.527885
  28. Sousa, J.J.T.; Goncalves, F.M.; Teixeira, J.P.. "IC defects-based testability analysis". 1992.
  29. Sousa, José T. de; Teixeira, J.P.. "Defect level estimation for digital ICs". 1992.
    10.1109/DFTVS.1992.224363
  30. Santos, M.B.; Goncalves, F.M.; Sousa, José T. de; Teixeira, J.P.. "Layout-level techniques for testability improvement of MOS physical designs". 1992.
  31. Sousa, J.J.T.; Goncalves, F.M.; Teixeira, J.P.. "High-quality physical designs of CMOS ICs". 1991.
    10.1109/EUASIC.1991.212846
  32. Santos, M.B.; Sousa, José T. de; Gonalves, F.M.; Teixeira, J.P.. "On the testability of realistic bridging faults". 1991.
    10.1109/DFTVS.1991.199959
Journal article
  1. Mário Véstias; Rui P. Duarte; José T. de Sousa; Horácio Neto. "Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units". ACM Transactions on Reconfigurable Technology and Systems (2023): https://doi.org/10.1145/3546182.
    10.1145/3546182
  2. David Mota; Helena Cruz; Pedro R. Miranda; Rui Policarpo Duarte; Jose T. de Sousa; Horacio C. Neto; Mario P. Vestias. "Onboard Processing of Synthetic Aperture Radar Backprojection Algorithm in FPGA". IEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensing (2022): https://doi.org/10.1109/JSTARS.2022.3169828.
    10.1109/JSTARS.2022.3169828
  3. Pedro R. Miranda; Daniel Pestana; João D. Lopes; Rui Policarpo Duarte; Mário P. Véstias; Horácio C. Neto; José T. de Sousa. "Configurable Hardware Core for IoT Object Detection". Future Internet 13 11 (2021): 280-280. https://doi.org/10.3390/fi13110280.
    10.3390/fi13110280
  4. João V. Roque; João D. Lopes; Mário P. Véstias; José T. de Sousa. "IOb-Cache: A High-Performance Configurable Open-Source Cache". Algorithms 14 8 (2021): 218-218. https://doi.org/10.3390/a14080218.
    10.3390/a14080218
  5. João D. Lopes; Mário P. Véstias; Rui Policarpo Duarte ; Horácio C. Neto; José T. de Sousa . "Coarse-Grained Reconfigurable Computing with the Versat Architecture". Electronics 10 6 (2021): 669-669. https://doi.org/10.3390/electronics10060669.
    10.3390/electronics10060669
  6. Daniel Pestana; Pedro R. Miranda; Joao D. Lopes; Rui P. Duarte; Mario P. Vestias; Horacio C. Neto; Jose T. De Sousa. "A Full Featured Configurable Accelerator for Object Detection With YOLO". IEEE Access 9 (2021): 75864-75877. https://doi.org/10.1109/ACCESS.2021.3081818.
    10.1109/ACCESS.2021.3081818
  7. Sousa, José T. de. "A fast and scalable architecture to run convolutional neural networks in low density FPGAs". Microprocessors and Microsystems (2020): http://dx.doi.org/10.1016/j.micpro.2020.103136.
    10.1016/j.micpro.2020.103136
  8. Mário P. Véstias; Rui Policarpo Duarte; José T. de Sousa; Horácio C. Neto. "Moving Deep Learning to the Edge". Algorithms 13 5 (2020): 125-125. https://doi.org/10.3390/a13050125.
    10.3390/a13050125
  9. Sousa, José T. de. "Accelerating PNG Encoding in Hardware". Jornadas Sobre Sistemas Reconfiguráveis (2020): https://zenodo.org/record/3679358.
    10.5281/ZENODO.3679358
  10. Sousa, José T. de; Mario P. Vestias; Rui P. Duarte; Jose T. De Sousa; Horacio C. Neto. "A Configurable Architecture for Running Hybrid Convolutional Neural Networks in Low-Density FPGAs". IEEE Access 8 (2020): 107229-107243. http://dx.doi.org/10.1109/access.2020.3000444.
    10.1109/access.2020.3000444
  11. Silva-Pereira, M.; De Sousa, J.T.; Freire, J.C.; Caldinhas Vaz, J.. "A 1.7-mW-92-dBm Sensitivity Low-IF Receiver in 0.13-µ m CMOS for Bluetooth le Applications". IEEE Transactions on Microwave Theory and Techniques 67 1 (2019): 332-346. http://www.scopus.com/inward/record.url?eid=2-s2.0-85055890213&partnerID=MN8TOARS.
    10.1109/TMTT.2018.2876224
  12. Véstias, M.P.; Duarte, R.P.; de Sousa, J.T.; Neto, H.C.. "Fast convolutional neural networks in low density FPGAs using zero-skipping and weight pruning". Electronics (Switzerland) 8 11 (2019): http://www.scopus.com/inward/record.url?eid=2-s2.0-85074702216&partnerID=MN8TOARS.
    10.3390/electronics8111321
  13. Sousa, José. "A 170 µtextA All-Digital GFSK Demodulator With Rejection of Low SNR Packets for Bluetooth-LE". IEEE Microwave and Wireless Components Letters 26 6 (2016): 452-454.
    10.1109/LMWC.2016.2562639
  14. Zuim, R.; De Sousa, J.T.; Coelho, C.N.. "Decision heuristic for Davis Putnam, Loveland and Logemann algorithm satisfiability solving based on cube subtraction". IET Computers and Digital Techniques 2 1 (2008): 30-39. http://www.scopus.com/inward/record.url?eid=2-s2.0-38649117895&partnerID=MN8TOARS.
    10.1049/iet-cdt:20060233
  15. Bhalla, A.; Lynce, I.; De Sousa, J.T.; Marques-Silva, J.. "Heuristic-based backtracking relaxation for propositional satisfiability". Journal of Automated Reasoning 35 1-3 (2005): 3-24. http://www.scopus.com/inward/record.url?eid=2-s2.0-33750323402&partnerID=MN8TOARS.
    10.1007/s10817-005-9005-y
  16. Cheung, P.Y.K.; Constantinides, G.A.; de Sousa, J.T.. "Guest editors' introduction: Field programmable logic and applications". IEEE Transactions on Computers 53 11 (2004): 1361-1362. http://www.scopus.com/inward/record.url?eid=2-s2.0-8744281469&partnerID=MN8TOARS.
    10.1109/TC.2004.97
  17. Bhalla, A; Lynce, I; de Sousa, JT; Marques-Silva, J. "Heuristic-based backtracking for propositional satisfiability". Lecture Notes in Computer Science (2003): https://publons.com/publon/3985467/.
    10.1007/978-3-540-24580-3_19
  18. Miron Abramovici; Jose T. de Sousa; Abramovici, M.; De Sousa, J.T.. "A SAT solver using reconfigurable hardware and virtual logic". Journal of Automated Reasoning 24 1-2 (2000): 5-36. https://publons.com/publon/14574574/.
    10.1023/A:1006310219368
  19. De Sousa, J.T.; Cheung, P.Y.K.. "Diagnosis of Boards for Realistic Interconnect Shorts". Journal of Electronic Testing: Theory and Applications (JETTA) 11 2 (1997): 157-171. http://www.scopus.com/inward/record.url?eid=2-s2.0-0031251071&partnerID=MN8TOARS.
    10.1023/A:1008270406603
  20. Sousa, José T. de; Gonçalves, F.M.; Paulo Teixeira, J.; Marzocca, C.; Corsi, F.; Williams, T.W.. "Defect level evaluation in an IC design environment". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 15 10 (1996): 1286-1293. http://www.scopus.com/inward/record.url?eid=2-s2.0-0030263876&partnerID=MN8TOARS.
    10.1109/43.541448
  21. Sousa, José T. de. "Physical design of testable CMOS digital integrated circuits". IEEE Journal of Solid State Circuits 26 7 (1991): 1064-1072.
    10.1109/4.92027

Intellectual property

Patent
  1. Sousa, José. 2012. "Reconfigurable coprocessor architecture template for nested loops and programming tool".
  2. Sousa, José T. de. 2011. "Network core access architecture". United States.
  3. Sousa, José T. de. 2002. "Virtual logic system for solving satisfiability problems using reconfigurable hardware". United States.
  4. Sousa, José T. de. 2001. "Parallel backtracing for satisfiability on reconfigurable hardware". United States.
Activities

Oral presentation

Presentation title Event name
Host (Event location)
2020/02/11 Sistemas integrados de código aberto, com processadores RISC-V e matrizes reconfiguráveis de granularidade grossa Jornadas sobre Sistemas Reconfiguráveis
Instituto Superior Técnico (Lisbon, Portugal)
2020/01/20 RISC-V/CGRA-based open source SoC 14th HiPEAC Workshop on Reconfigurable Computing (WRC'2020)
HIPEAC (Bologna, Italy)
2016/11/18 Versat, a Runtime Partially Reconfigurable Coarse-Grain Reconfigurable Array using a Programmable Controller, Invited Talk, 18/11/2016, FEUP - Universidade do Porto, Portugal Invited Talk
FEUP - Universidade do Porto (Porto, Portugal)
2014/10/08 Reconfigurable Data Stream Architectures in Industrial Audio Processing. DASIP 2014 Conference on Design & Architectures for Signal & Image Processing
Escuela Técnica Superior de Ingenieros Industriales de Madrid (Madrid, Spain)
2012/03 Sistemas de áudio integrados utilizando multi-processadores, Lisboa, Portugal, March, 2012. Jornadas de Engenharia Electrotécnica e de Computadores
Instituto Superior Técnico (Lisbon, Portugal)
2010/03 Propriedade Intelectual Jornadas de Engenharia Electrotécnica e de Computadores
Instituto Superior Técnico (Lisbon, Portugal)
2010 Application Processors and Digital Signal Processor Ciência 2010
FCT (Lisbon, Portugal)
2007/02 Reconfiguration Starts at the IP Level Jornadas de Engenharia Electrotécnica e de Computadores
Instituto Superior Técnico (Lisbon, Portugal)
2003/04 DARP - a Digital Audio Reconfigurable Processor, Paris, France, April 2003. Invited Talk
Laboratoire Informatique de Paris 6 (LIP6), Université Pierre et Marie Currie (Paris, France)
2001/05 A Configware/Software Approach to SAT Solving Invited Talk
Bell Labs-Lucent Technologies (Murray Hill, N.J., United States)
1999/05 Satisfiability on Reconfigurable Hardware Invited Talk
University of California at Berkeley (Berkeley, CA, United States)
1997/05 Diagnosis of Realistic Defects in Electronic Assemblies Outstanding Research Seminar Series
Department of Electrical and Electronic Engineering, Imperial College of Science, Technology and Medicine (London, United Kingdom)

Supervision

Thesis Title
Role 		Degree Subject (Type)
Institution / Organization
2004 - 2007 Uma heurística de decisão baseada na subtração de cubos para solucionadores DPLL do problema de satisfabilidade
Co-supervisor of Romanelli Lodron Zuim
 Computer Science (PhD)
Universidade Federal de Minas Gerais, Brazil
2002 - 2006 Heuristic-Based Backtracking Relaxation for Propositional Satisfiability
Supervisor
 Computer Science (PhD)
Universidade de Lisboa Instituto Superior Técnico, Portugal

Event organisation

Event name
Type of event (Role) 		Institution / Organization
2023/07/19 - Current 34th IEEE International Conference on Application-specific Systems, Architectures and Processors (2023/07/19 - 2023/07/21)
Conference (Member of the Organising Committee)
 Universidade do Porto Faculdade de Engenharia, Portugal
2003/09 - Current Field Programmable Logic and Application: 13th International Conference, FPL 2003, Lisbon, Portugal (2003/09/01 - 2003/09/03)
Conference (President of the Organising Committee)
 Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa, Portugal

Association member

Society Organization name Role
1999 - Current IEEE
Distinctions

Title

2021 IEEE Senior Member

Other distinction

2019 Excellent Teacher
Universidade de Lisboa Instituto Superior Técnico, Portugal
2017 Best paper award
2010 Design Vision Award
International Engineering Consortium, United States
1997 Outstanding Research Award